发明授权
- 专利标题: Method for self-aligning polysilicon gates with field isolation and the resultant structure
- 专利标题(中): 使用场隔离自对准多晶硅栅极的方法及其结果
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申请号: US985400申请日: 1997-12-05
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公开(公告)号: US6046088A公开(公告)日: 2000-04-04
- 发明人: Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
- 申请人: Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
- 申请人地址: CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: CA Sunnyvale
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/336 ; H01L21/762
摘要:
A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.
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