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    Method and test structure for characterizing sidewall damage in a semiconductor device
    1.
    发明授权
    Method and test structure for characterizing sidewall damage in a semiconductor device 失效
    用于表征半导体器件中侧壁损伤的方法和测试结构

    公开(公告)号：US06600333B1

    公开(公告)日：2003-07-29

    申请号：US09501958

    申请日：2000-02-10

    申请人： Jeremy I. Martin ,  Nicholas J. Kepler ,  Larry L. Zhao

    发明人： Jeremy I. Martin ,  Nicholas J. Kepler ,  Larry L. Zhao

    IPC分类号： G01R2726

    CPC分类号： H01L22/34 ,  G01R31/2884

    摘要： A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared. Damage to the insulative layer is characterized based on the comparison.

    摘要翻译： 测试电路包括晶片，形成在晶片上的绝缘层，以及形成在绝缘层中的多个测试结构。 每个测试结构包括具有第一多个指状物的第一梳子和具有第二多个指状物的第二梳子。 手指的第一和第二多个交织以限定第一和第二多个手指之间的手指间隔。 测试结构中第一个测试结构中的手指间距不同于第二个测试结构中的手指间距。 用于表征半导体器件中的损伤的方法包括提供具有绝缘层的晶片和形成在绝缘层中的多个测试结构。 测试结构具有不同的几何形状。 确定多个测试结构的第一和第二测试结构的电特性。 比较第一和第二测试结构的电气特性。 基于比较，对绝缘层的损伤进行了表征。

    Forming minimal size spaces in integrated circuit conductive lines
    6.
    发明授权
    Forming minimal size spaces in integrated circuit conductive lines 失效
    在集成电路导线中形成最小尺寸空间

    公开(公告)号：US5930659A

    公开(公告)日：1999-07-27

    申请号：US986098

    申请日：1997-12-05

    申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/324

    CPC分类号： H01L21/76888 ,  H01L21/32105 ,  H01L21/76838

    摘要： A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.

    摘要翻译： 通过将多晶硅中期望的间隙或空间的大小的面积转换为氧化硅，然后除去氧化硅，形成多晶硅导电线图形中的最小间隙或间隔的方法，以增加集成电路的密度。 优选的方法是选择性地将氧注入到多晶硅中并进行退火以将氧注入的多晶硅转化为氧化硅。 作为替代方法，首先通过常规光学光刻形成覆盖在导电线上的绝缘层中的开口，随后在开口中形成侧壁以形成减小的开口，并且使用侧壁作为掩模，以通过缩小开口来覆盖氧气注入氧气 并进入暴露的多晶硅导电线。 在退火之后，注入的多晶硅转变成氧化硅并去除，以在多晶硅导电线图案中形成与缩小的开口大致相等的间隙或空间。 代替用氧气进行全面注入，可以使用热氧化来将暴露的多晶硅转化为氧化硅。

    Semiconductor device with partial passivation layer
    7.
    发明授权
    Semiconductor device with partial passivation layer 有权
    具有部分钝化层的半导体器件

    公开(公告)号：US06313538B1

    公开(公告)日：2001-11-06

    申请号：US09489479

    申请日：2000-01-21

    申请人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    发明人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.

    摘要翻译： 半导体器件包括第一电介质层，形成在第一电介质层中的多个导电互连，形成在导电互连之上的图案化钝化层，以及形成在钝化层和第一介电层上方并与钝化层接触的第二介电层 。 一种用于形成半导体器件的方法包括提供基底层，在基底层上形成第一介电层，在第一介电层中形成多个导电互连，在导电互连之上形成图案化的钝化层，以及形成第二电介质 并且与钝化层和第一介电层接触。

    Method for self-aligning polysilicon gates with field isolation and the resultant structure
    10.
    发明授权
    Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效
    使用场隔离自对准多晶硅栅极的方法及其结果

    公开(公告)号：US6046088A

    公开(公告)日：2000-04-04

    申请号：US985400

    申请日：1997-12-05

    申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/6659

    摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

    摘要翻译： 在诸如浅​​氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。