发明授权
US6061764A Coherent variable length reads which implicates multiple cache lines by
a memory controller connected to a serial and a pipelined bus utilizing
a plurality of atomic transactions
失效
相干可变长度读取，其涉及连接到串行和流水线总线的存储器控制器使用多个原子事务的多个高速缓存行
- 专利标题： Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions
- 专利标题（中）： 相干可变长度读取，其涉及连接到串行和流水线总线的存储器控制器使用多个原子事务的多个高速缓存行
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申请号： US13097申请日： 1998-01-26
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公开(公告)号： US6061764A公开(公告)日： 2000-05-09
- 发明人: Suresh Chittor , Chih-Cheh Chen , Sin Sim Tan , Jonathan Nick Spitz
- 申请人： Suresh Chittor , Chih-Cheh Chen , Sin Sim Tan , Jonathan Nick Spitz
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： G06F12/02
- IPC分类号： G06F12/02 ; G06F12/06 ; G06F13/16
摘要：
Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.
公开/授权文献
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