- 专利标题: Branch prediction device with two levels of branch prediction cache
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申请号: US638389申请日: 1996-04-26
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公开(公告)号: US6067616A公开(公告)日: 2000-05-23
- 发明人: David R. Stiles , John G. Favor , Korbin S. Van Dyke
- 申请人: David R. Stiles , John G. Favor , Korbin S. Van Dyke
- 申请人地址: CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: CA Sunnyvale
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F9/30
摘要:
An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.
公开/授权文献
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