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    Two-level branch prediction cache
    1.
    发明授权
    Two-level branch prediction cache 失效
    两级分支预测缓存

    公开(公告)号：US5327547A

    公开(公告)日：1994-07-05

    申请号：US954441

    申请日：1992-09-30

    申请人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    发明人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00

    CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3848

    摘要： An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

    摘要翻译： 利用混合缓存结构的改进的分支预测高速缓存（BPC）方案。 BPC提供两级分支信息缓存。 完全关联的第一级BPC是浅而宽的结构（36个32字节的条目），其缓存有限数量的分支指令的全部预测信息。 第二个直接映射级别BPC是一个深而窄的结构（256个2字节条目），它仅缓存部分预测信息，但对于大量的分支指令则是这样做的。 当每个分支指令被取出和解码时，其地址用于在两个分支预测高速缓存中执行并行查找。

    Branch prediction device with two levels of branch prediction cache
    2.
    发明授权
    Branch prediction device with two levels of branch prediction cache 失效
    分支预测装置具有两级分支预测缓存

    公开(公告)号：US06425075B1

    公开(公告)日：2002-07-23

    申请号：US09361809

    申请日：1999-07-27

    申请人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    发明人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    IPC分类号： G06F1200

    CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3848

    摘要： An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

    摘要翻译： 利用混合缓存结构的改进的分支预测高速缓存（BPC）方案。 BPC提供两级分支信息缓存。 完全关联的第一级BPC是浅而宽的结构（36个32字节的条目），其缓存有限数量的分支指令的全部预测信息。 第二个直接映射级别BPC是一个深而窄的结构（256个2字节条目），它仅缓存部分预测信息，但对于大量的分支指令则是这样做的。 当每个分支指令被取出和解码时，其地址用于在两个分支预测高速缓存中执行并行查找。

    Two-level branch prediction cache
    3.
    发明授权
    Two-level branch prediction cache 失效
    两级分支预测缓存

    公开(公告)号：US5515518A

    公开(公告)日：1996-05-07

    申请号：US270855

    申请日：1994-07-05

    申请人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    发明人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3848

    摘要： AN improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

    摘要翻译： AN改进的使用混合高速缓存结构的分支预测高速缓存（BPC）方案。 BPC提供两级分支信息缓存。 完全关联的第一级BPC是浅而宽的结构（36个32字节的条目），其缓存有限数量的分支指令的全部预测信息。 第二个直接映射级别BPC是一个深而窄的结构（256个2字节条目），它仅缓存部分预测信息，但对于大量的分支指令则是这样做的。 当每个分支指令被取出和解码时，其地址用于在两个分支预测高速缓存中执行并行查找。

    Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
    4.
    发明授权
    Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence 失效
    缓存记录系统，用于根据指令序列动态地改变单个高速缓存存储器线路作为分支目标输入或前缀指令队列

    公开(公告)号：US5230068A

    公开(公告)日：1993-07-20

    申请号：US485304

    申请日：1990-02-26

    申请人： Korbin S. Van Dyke ,  David R. Stiles ,  John G. Favor

    发明人： Korbin S. Van Dyke ,  David R. Stiles ,  John G. Favor

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3808

    摘要： A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while certain entries function as instruction queues.By using parts of the BTC to serve as instruction queues, the inefficiency of separate queue structures is eliminated and the queues are implemented with the greater device density characteristic of the RAM structure which the BTC core is based on. This merging of these structures also substantially simplifies the instruction queue control and the routing of instruction words between BTC entries and queues.

    摘要翻译： 将高性能CPU设计的多个指令队列和分支目标缓存（BTC）集成到单个物理结构中的系统。 有效地，队列以这样一种方式被合并到BTC中：在任何时间点，这个结构的大部分用作BTC，而某些条目用作指令队列。 通过使用BTC的部分作为指令队列，消除了单独队列结构的低效率，并且使用BTC核心所基于的RAM结构的更大的器件密度特性来实现队列。 这些结构的合并也大大简化了指令队列控制和BTC条目和队列之间的指令字的路由。

    Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence
    6.
    发明授权
    Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence 失效
    高速缓冲存储器系统，用于基于指令序列动态地将单个高速缓冲存储器线改变为分支目标入口或预取指令队列

    公开(公告)号：US5748932A

    公开(公告)日：1998-05-05

    申请号：US378054

    申请日：1995-01-25

    申请人： Korbin S. Van Dyke ,  David R. Stiles ,  John G. Favor

    发明人： Korbin S. Van Dyke ,  David R. Stiles ,  John G. Favor

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/30

    CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3808

    摘要： A processor with a branch target cache (BTC) and multiple instruction prefetch storage circuits. A control mechanism allows the fetching of instructions to be transferred from a first prefetch storage circuit to a second prefetch storage circuit which contains branch target instruction bytes. The control is transferred based on a prediction of whether the branch will be taken using history bits associated with the branch instruction. If the processor later determines that the branch is mispredicted, the execution of instructions resumes from the first prefetch storage circuit.

    摘要翻译： 具有分支目标缓存（BTC）和多个指令预取存储电路的处理器。 控制机制允许将指令的取出从第一预取存储电路传送到包含分支目标指令字节的第二预取存储电路。 基于使用与分支指令相关联的历史比特是否将分支进行的预测来传送控制。 如果处理器稍后确定分支被错误预测，则指令的执行从第一预取存储电路恢复。

    Two-level branch prediction cache
    7.
    发明授权
    Two-level branch prediction cache 失效
    两级分支预测缓存

    公开(公告)号：US5163140A

    公开(公告)日：1992-11-10

    申请号：US844995

    申请日：1992-03-02

    申请人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    发明人： David R. Stiles ,  John G. Favor ,  Korbin S. Van Dyke

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3806 ,  G06F9/3804 ,  G06F9/3848

    摘要： An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

    摘要翻译： 利用混合缓存结构的改进的分支预测高速缓存（BPC）方案。 BPC提供两级分支信息缓存。 完全关联的第一级BPC是浅而宽的结构（36个32字节的条目），其缓存有限数量的分支指令的全部预测信息。 第二个直接映射级别BPC是一个深而窄的结构（256个2字节条目），它仅缓存部分预测信息，但对于大量的分支指令则是这样做的。 当每个分支指令被取出和解码时，其地址用于在两个分支预测高速缓存中执行并行查找。