发明授权
US6069574A Hadamard code generation circuit 失效
哈达玛码生成电路

Hadamard code generation circuit
摘要:
A hadamard code generation circuit is disclosed. The circuit includes a start reset signal generator for generating a start reset signal START.sub.-- RESET when a 6-bit output signal REF.sub.-- C from the 6-bit reference counter, a higher 4-bit index output signal H(5:2) of the 6-bit register and a 2-bit value from a ground circuit are identical; a "0" value force allocation unit for outputting a FORCE.sub.-- 0.sub.-- DEL signal for forcibly allocating all values of the 0th column to "0" when a 4-bit output signal REF.sub.-- C (5:2) from the 6-bit reference counter and a 4-bit value from the ground circuit are identical; a 2-bit counter for receiving the start reset signal and an external clock signal, outputting lowest bit signals C1 and C0 and outputting a carry-out signal; a 4-bit counter operated in accordance with a result that an inverted FORCE.sub.-- 0 signal and a carry-out signal are ANDed and outputting higher bit signals C4, C3 and C2; a 4th hadamard code generator for logically processing a lower 2-bit output signal from the 2-bit counter and a lower 2-bit index value from the 6-bit register and generating a 4-th hadamard code; a 12th paley code generator for generating a 12th paley code using an output signal from the counter and the FORCE.sub.-- 0.sub.-- DEL signal and the ALL.sub.-- ZERO signal; and a 48th hadamard code generator for logically processing a 4th hadamard code and a 12th paley code and generating a 48th hadamard code.
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