A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.