公开(公告)号：US20100261324A1

公开(公告)日：2010-10-14

申请号：US12802894

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US20100259985A1

公开(公告)日：2010-10-14

申请号：US12802895

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US07382662B2

公开(公告)日：2008-06-03

申请号：US11409247

申请日：2006-04-21

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C11/34 ,  H01L23/58

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

摘要翻译： 本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。 控制栅极和字栅之间的垂直绝缘体不包括氮化物层。 这样可以防止电子捕获的问题。 可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。 该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。 双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

公开(公告)号：US20080101117A1

公开(公告)日：2008-05-01

申请号：US11982172

申请日：2007-11-01

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US07359250B2

公开(公告)日：2008-04-15

申请号：US11409333

申请日：2006-04-21

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C11/34

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

公开(公告)号：US20070114597A1

公开(公告)日：2007-05-24

申请号：US11652888

申请日：2007-01-12

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： H01L29/792

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

摘要翻译： 本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。 控制栅极和字栅之间的垂直绝缘体不包括氮化物层。 这样可以防止电子捕获的问题。 可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。 该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。 双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

公开(公告)号：US07149126B2

公开(公告)日：2006-12-12

申请号：US10756568

申请日：2004-01-13

申请人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115

摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

摘要翻译： 描述了一种快速低电压弹道程序，超短通道，超高密度双位多级闪存。 本发明的结构和操作通过具有小于40nm的超短控制栅极通道的双重MONOS单元结构实现，具有提供高电子注入效率的弹道注入和在3〜5V的低编程电压下非常快速的程序 。 弹道MONOS存储单元被布置在以下阵列中：每个存储单元包含用于一个字门的两个氮化物区域，以及1/2扩散源和1/2位扩散。 控制门可以单独定义，也可以通过相同的扩散共享。 扩散在单元之间共享并且平行于侧壁控制栅极并垂直于字线。

公开(公告)号：US06982456B2

公开(公告)日：2006-01-03

申请号：US10889013

申请日：2004-07-13

申请人： Nobuyo Sugiyama ,  Hiromasa Fujimoto ,  Shinji Odanaka ,  Seiki Ogura

发明人： Nobuyo Sugiyama ,  Hiromasa Fujimoto ,  Shinji Odanaka ,  Seiki Ogura

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween. Within the semiconductor substrate and in the vicinity of the stepped portion, there is formed a depletion control layer which is composed of a heavily doped impurity region and formed to extend from a position located under the floating gate electrode and at a distance from the upper corner of the stepped portion toward the lower corner of the stepped portion and adjoin the end portion of a drain region without reaching a step side region.

公开(公告)号：US06770931B2

公开(公告)日：2004-08-03

申请号：US10366420

申请日：2003-02-14

申请人： Nobuyo Sugiyama ,  Hiromasa Fujimoto ,  Shinji Odanaka ,  Seiki Ogura

发明人： Nobuyo Sugiyama ,  Hiromasa Fujimoto ,  Shinji Odanaka ,  Seiki Ogura

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween. Within the semiconductor substrate and in the vicinity of the stepped portion, there is formed a depletion control layer which is composed of a heavily doped impurity region and formed to extend from a position located under the floating gate electrode and at a distance from the upper corner of the stepped portion toward the lower corner of the stepped portion and adjoin the end portion of a drain region without reaching a step side region.

公开(公告)号：US06707079B2

公开(公告)日：2004-03-16

申请号：US10356446

申请日：2003-02-03

申请人： Kumihiro Satoh ,  Seiki Ogura ,  Tomoya Saito

发明人： Kumihiro Satoh ,  Seiki Ogura ,  Tomoya Saito

IPC分类号： H01L2976

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/7923 ,  Y10S257/906 ,  Y10S438/954

摘要： Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.

摘要翻译： 在本发明中提出了一种用于集成双MONOS存储单元阵列和CMOS逻辑器件电路的高密度双MONOS存储器件的制造方法及其阵列组织。 本发明由两种制造方法组成：i）同时定义存储器栅极和逻辑门，从而改进工艺集成方案，以便更容易和更可靠的制造.ii）位线跨越字门和控制栅极。 本发明着重于降低寄生薄片电阻以实现高速同时保持低的制造成本。 双MONOS单元将存储器存储在选择栅极的两个侧壁上的两个共享控制栅极下的两个氮化物存储单元元件中。 该方法适用于具有平坦通道的设备和/或具有步进通道的设备。本发明的两个实施例被公开。