发明授权
US6087864A Digital frequency multiplier circuit including delay circuit 失效
数字倍频电路包括延时电路

Digital frequency multiplier circuit including delay circuit
摘要:
A frequency multiplier circuit device having a delay circuit including a plurality of delay elements, and a selector circuit for selecting the number of delay elements for every output stage of the delay circuit. A reference input signal and an output from the selector circuit for determining the period of the reference input signal are input to a phase comparator. The selector circuit is controlled on the basis of an output from the phase comparator to select the number of delay elements of the delay circuit, so as to generate a signal for multiplying a frequency by N, so that the signal is supplied to an exclusive NOR circuit to output a signal having a frequency an N-number of times that of the reference input signal.
公开/授权文献
信息查询
0/0