发明授权
- 专利标题: Digital frequency multiplier circuit including delay circuit
- 专利标题(中): 数字倍频电路包括延时电路
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申请号: US967106申请日: 1997-11-10
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公开(公告)号: US6087864A公开(公告)日: 2000-07-11
- 发明人: Akira Aoki
- 申请人: Akira Aoki
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX8-312609 19961111
- 主分类号: H03B19/00
- IPC分类号: H03B19/00 ; H03K5/00 ; H03K5/13 ; H03L7/08 ; H03L7/081 ; H03L7/16
摘要:
A frequency multiplier circuit device having a delay circuit including a plurality of delay elements, and a selector circuit for selecting the number of delay elements for every output stage of the delay circuit. A reference input signal and an output from the selector circuit for determining the period of the reference input signal are input to a phase comparator. The selector circuit is controlled on the basis of an output from the phase comparator to select the number of delay elements of the delay circuit, so as to generate a signal for multiplying a frequency by N, so that the signal is supplied to an exclusive NOR circuit to output a signal having a frequency an N-number of times that of the reference input signal.
公开/授权文献
- US5257595A Flag system 公开/授权日:1993-11-02
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