- 专利标题: Shared memory multiprocessor performing cache coherency
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申请号: US30957申请日: 1998-02-26
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公开(公告)号: US6088770A公开(公告)日: 2000-07-11
- 发明人: Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
- 申请人: Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX9-059914 19970227
- 主分类号: G06F15/177
- IPC分类号: G06F15/177 ; G06F12/02 ; G06F12/08 ; G06F15/17 ; G06F13/14
摘要:
A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.
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