公开(公告)号：US06606688B1

公开(公告)日：2003-08-12

申请号：US09642002

申请日：2000-08-21

申请人： Masaru Koyanagi ,  Disuke Yamane ,  Hideya Akashi ,  Yuji Tsushima ,  Tadayuki Sakakibara

发明人： Masaru Koyanagi ,  Disuke Yamane ,  Hideya Akashi ,  Yuji Tsushima ,  Tadayuki Sakakibara

IPC分类号： G06F1200

CPC分类号： G06F12/0862

摘要： A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.

摘要翻译： 缓存控制器存储用于预取块大小和步幅值的预设变量。 缓存控制器从处理器接收对主存储器的访问请求，并且基于访问请求和变量生成预取请求。 高速缓存控制器基于生成的预取请求从主存储器读取数据，并将该数据写入缓存存储器。

公开(公告)号：US06591325B1

公开(公告)日：2003-07-08

申请号：US09547392

申请日：2000-04-11

申请人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1314

CPC分类号： G06F13/4204

摘要： An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.

摘要翻译： 一种在多个系统模块之间传送交易的信息处理系统。 请求侧模块中的请求侧接口单元具有请求ID队列，其中发出的请求事务按照发布的顺序存储。 请求侧队列指针指向与要接受的响应事务相对应的该请求ID队列中的条目。 响应侧模块中的响应侧接口单元具有响应队列，其中接受请求事务按接受顺序存储。 响应侧队列指针指向对应于接下来要发出的响应事务的该响应队列中的条目。 因此，在请求侧接口单元和响应侧接口单元之间传送请求事务和相应的响应事务，而不转移事务ID。 当响应顺序改变时，响应侧接口单元发出改变请求侧队列指针的值的命令，以通知请求侧接口单元的顺序改变。

公开(公告)号：US07206818B2

公开(公告)日：2007-04-17

申请号：US10632856

申请日：2003-08-04

申请人： Toshio Okochi ,  Toru Shonai ,  Naoki Hamanaka ,  Naohiko Irie ,  Hideya Akashi

发明人： Toshio Okochi ,  Toru Shonai ,  Naoki Hamanaka ,  Naohiko Irie ,  Hideya Akashi

IPC分类号： G06F15/167

CPC分类号： G06F15/167 ,  G06F2212/682

摘要： Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.

摘要翻译： 在每个处理器中具有翻译后备缓冲器（TLB）的多处理器系统，并具有用于避免TLB清除开销的结构。 每个处理器节点设置有部分主存储器和物理页映射表（PPT）。 PPT存储主存储器的物理页数和虚拟页码之间的映射。 其他节点的每个内存访问事务都指定物理地址和虚拟页码。 访问目的地节点不是通过广播TLB清除事务来严格维护TLB一致性，而是在接收事务时检查在存储器访问事务中指定的虚拟页号与在PPT中映射的虚拟页号之间的一致性。 如果两者都一致，则执行存储器访问。 如果不一致，则将错误消息传送到请求访问源。

公开(公告)号：US06874053B2

公开(公告)日：2005-03-29

申请号：US10654983

申请日：2003-09-05

申请人： Yoshiko Yasuda ,  Naoki Hamanaka ,  Toru Shonai ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara

发明人： Yoshiko Yasuda ,  Naoki Hamanaka ,  Toru Shonai ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara

IPC分类号： G06F12/08 ,  G06F15/173 ,  G06F13/00 ,  G06F15/167

CPC分类号： G06F12/0813 ,  G06F12/0833 ,  G06F2212/1016

摘要： Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.

摘要翻译： 每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器，基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息 是否需要节点信息和传输目的地的单位信息，并将这些信息添加到访问请求。 用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息，节点信息和添加到访问请求的单元信息。 当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时，节点间连接电路将访问请求传送到不是直接连接节点的节点间连接电路 到由单位信息指定的单位。

公开(公告)号：US06516391B1

公开(公告)日：2003-02-04

申请号：US09523737

申请日：2000-03-13

申请人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1200

CPC分类号： G06F12/0813 ,  G06F12/0817 ,  G06F15/177 ,  G06F2212/2542

摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

摘要翻译： 在根据其中包含多个处理器单元的多个处理器节点经由网络彼此耦合的NUMA或UMA而布置的多处理器中，结合存储器访问操作执行的高速缓存侦听操作在两个阶段 即在节点内执行的本地侦听操作，以及节点之间的全局侦听操作。 在执行本地侦听操作之前，向具有存储器的目标节点发出用于指定存储器的RAS的ACTV命令，并且预先激活存储器访问。 另外指定存储器的CAS，并且在发出ACTV命令之后重新执行存储器访问，然后发出存储器访问命令。 当存在待访问的存储器存在除了源节点之外的处理器节点的可能性时，该存储器访问命令被发布以分发给所有节点，以便执行全局侦听操作。 另一方面，当不存在要访问的存储器被缓存时，该存储器访问命令仅以一对一对应的方式传送到目标节点。

公开(公告)号：US06295579B1

公开(公告)日：2001-09-25

申请号：US09070851

申请日：1998-05-01

申请人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

发明人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

IPC分类号： G06F1200

CPC分类号： G06F12/0813 ,  G06F12/0848 ,  G06F2212/272

摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

摘要翻译： 并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。 并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。 每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

公开(公告)号：US6119150A

公开(公告)日：2000-09-12

申请号：US789184

申请日：1997-01-24

申请人： Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

发明人： Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

IPC分类号： G06F15/17 ,  G06F12/08 ,  G06F15/167 ,  G06F13/00

CPC分类号： G06F12/0837 ,  G06F12/0813

摘要： An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

摘要翻译： 采用根据来自存储控制器的请求执行高速缓存一致性控制的指令处理器。 存储控制器设置有高速缓存一致性控制处理电路，其对作为通过数据传送发生的主存储器访问的目的地的地址执行高速缓存一致性控制。 同时，高速缓存一致性控制处理电路在数据传送过程中对每条高速缓存线执行一次高速缓存一致性控制处理。 消除了与数据传输有关的软件执行的高速缓存一致性控制处理，提高了包括缓存存储器控制在内的数据传输效率，并减少了对程序的限制。

公开(公告)号：US06839806B2

公开(公告)日：2005-01-04

申请号：US09941696

申请日：2001-08-30

申请人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

发明人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0855 ,  G06F12/0831

摘要： A cache system comprising a cache tag buffer 270 for storing a part of a cache tag memory 260. When a memory processing request is issued from a processor 10, a cache control means 280 retrieves both of the cache tag memory 260 and the cache tag buffer 270. If a target cache block is present in the cache tag buffer 270, then, without waiting for a retrieval result of the cache tag memory 260, the cache control circuit 280 accesses the cache data memory 250 using information of the cache block.

公开(公告)号：US06789173B1

公开(公告)日：2004-09-07

申请号：US09585390

申请日：2000-06-02

申请人： Tsuyoshi Tanaka ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai

发明人： Tsuyoshi Tanaka ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.

摘要翻译： 在具有通过信号线彼此连接的多个节点的主存储器共享类型的多处理器系统中; 所述多个节点中的每一个包括其中具有高速缓存的CPU，主存储器和节点控制器，用于执行CPU，主存储器以及除了其自身节点之外的节点之间的通信控制。 节点控制器具有用于控制多个节点之间的通信接口的通信控制器，用于确定从多个节点中的至少一个节点发出的指向多个节点的主存储器的存储器访问的处理顺序的交叉开关， 和横杆控制器使横梁有效或无效。

公开(公告)号：US06636926B2

公开(公告)日：2003-10-21

申请号：US09740816

申请日：2000-12-21

申请人： Yoshiko Yasuda ,  Naoki Hamanaka ,  Toru Shonai ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara

发明人： Yoshiko Yasuda ,  Naoki Hamanaka ,  Toru Shonai ,  Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara

IPC分类号： G06F1300

CPC分类号： G06F12/0813 ,  G06F12/0833 ,  G06F2212/1016

摘要： Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

摘要翻译： 每个节点包括用于解码由处理器或I / O设备发出的访问请求的控制信息和地址信息的节点控制器，基于解码结果生成指示高速缓存一致性控制的高速缓存一致性控制信息 是否需要节点信息和传输目的地的单位信息，并将这些信息添加到访问请求。 用于连接节点控制器中的单元的节点内连接电路保持高速缓存一致性控制信息，节点信息和添加到访问请求的单元信息。 当高速缓存一致性控制信息指示不需要高速缓存一致性控制并且节点信息指示本地节点时，节点内连接电路不是将互连节点的节点间连接电路的访问请求传送到节点间连接电路，而是直接连接到 单位由单位信息指定。