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1.发明授权Computer system, information collection support device, and method for supporting information collection 有权计算机系统，信息收集支持设备和信息收集支持方法公开(公告)号：US08234584B2
公开(公告)日：2012-07-31
申请号：US12379283
申请日：2009-02-18
申请人： Masahiro Motobayashi , Toshio Okochi , Michiko Sakai , Maki Hayashi , Akio Azuma
发明人： Masahiro Motobayashi , Toshio Okochi , Michiko Sakai , Maki Hayashi , Akio Azuma
CPC分类号： G06F17/30867
摘要： Provided is a computer system including an information providing server and a computer which is coupled to the information providing server, and which collects information, the computer being configured to: record status histories including a history of an operation to a screen which shows a status of the computer, and which is displayed on the computer in chronological order to constitute a set of the status histories; and divide, in a case where a history of an operation of switching the screen is detected from the set of the status histories, based on the history of the operation of switching the screen, the set of the status histories. Accordingly, when a user collects information, navigation information is provided by taking the fact that the user has actually reached useful information into consideration.
摘要翻译： 提供了一种包括信息提供服务器和计算机的计算机系统，其耦合到信息提供服务器并且收集信息，该计算机被配置为：将包括操作历史的状态历史记录到显示状态 计算机，并按时间顺序显示在计算机上，构成一组状态历史; 并且根据状态历史的集合，根据切换屏幕的操作的历史来检测状态历史的集合，从而从屏幕的一组中检测到切换屏幕的操作的历史的情况。 因此，当用户收集信息时，通过考虑用户实际上已经考虑到有用信息的事实来提供导航信息。
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公开(公告)号：US20070195949A1
公开(公告)日：2007-08-23
申请号：US11653879
申请日：2007-01-17
IPC分类号： H04L9/28
CPC分类号： H04L9/003 , G06F21/72 , G06F21/75 , G06F21/755 , H04L2209/122
摘要： An increase in safety from attacks by use of hardware-like methods by small-sized hardware is achieved. An encryption processing device includes a logical circuit capable of programmably setting logics for executing cipher processing, a memory that stores plural pieces of logical configuration information corresponding to an identical cipher processing algorithm, and a CPU that selectively sets plural logics corresponding to an identical cipher processing algorithm in the logical circuit. Even in processing using an identical cipher key, by changing the logic of the logical circuit for each processing, power consumption in cipher processing can be varied, and places a timing in which malfunctions occur can be varied. Moreover, an increase in the scale of hardware for realizing plural logics can be curbed.
摘要翻译： 实现了通过使用小型硬件的类似硬件的方法的攻击来提高安全性。 加密处理装置包括能够可编程地设置用于执行密码处理的逻辑的逻辑电路，存储与相同密码处理算法相对应的多条逻辑配置信息的存储器，以及选择性地设置与相同的密码处理对应的多个逻辑的CPU 算法在逻辑电路中。 即使在使用相同的加密密钥的处理中，通过改变每个处理的逻辑电路的逻辑，可以改变密码处理中的功耗，并且可以改变发生故障的定时。 此外，可以抑制用于实现多个逻辑的硬件规模的增加。
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3.发明授权Method for protection of sensor node's data, a systems for secure transportation of a sensor node and a sensor node that achieves these 失效用于保护传感器节点数据的方法，用于传感器节点和实现这些传感器节点的传感器节点的安全传输的系统公开(公告)号：US07693675B2
公开(公告)日：2010-04-06
申请号：US11806966
申请日：2007-06-05
申请人： Masahiro Motobayashi , Akiko Sato , Toshio Okochi
发明人： Masahiro Motobayashi , Akiko Sato , Toshio Okochi
IPC分类号： G01R29/00
CPC分类号： H04L63/0428 , H04L63/0869 , H04L67/12
摘要： Methods of confidential data sharing and mutual authentication between a sensor node and a router are established, and data in the sensor node is protected from a physical attack. Sensor node issuing processing is performed on a sensor node having a tamper resistant device. The sensor node issuing processing is processing in which data and a function that are deactivated are loaded in the tamper resistant device of the sensor node from the time of manufacture of the sensor node to the time the sensor node reaches a system that runs the sensor node. Activation data is used to activate the deactivated data and function. The activation data is shared between stages of the issuing processing with the use of a data management system.
摘要翻译： 建立传感器节点与路由器之间机密数据共享和相互认证的方法，保护传感器节点中的数据免受物理攻击。 在具有防篡改设备的传感器节点上执行传感器节点发布处理。 传感器节点发布处理是从传感器节点的制造时到传感器节点到达传感器节点的系统的时刻将被去激活的数据和功能加载到传感器节点的防篡改设备中的处理 。 激活数据用于激活停用的数据和功能。 激活数据在使用数据管理系统的发行处理的阶段之间共享。
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公开(公告)号：US07664939B2
公开(公告)日：2010-02-16
申请号：US11734361
申请日：2007-04-12
摘要： A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is written in a memory, and in the case when the control transits from the code block to other code block, by use of code block operation values obtained beforehand from these two code block IDs thereof, the code block ID in the memory is updated, and it is judged whether the updated code block ID in the memory and the code block ID allotted to the code block as the execution objective are identical or not so that a control flow error is detected.
摘要翻译： 要由计算机执行的程序被分成多个代码块，并且将唯一的代码块ID分配给每个代码块。 在开始执行程序的时刻，与执行开始地址相对应的代码块ID被写入存储器中，并且在控制从代码块转移到其他代码块的情况下，通过使用代码块 从这两个代码块ID预先获得的操作值，存储器中的代码块ID被更新，并且判断存储器中更新的代码块ID和作为执行目标分配给代码块的代码块ID是否是 相同或不相同，从而检测到控制流量错误。
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5.发明申请公开(公告)号：US20090254740A1
公开(公告)日：2009-10-08
申请号：US12417856
申请日：2009-04-03
申请人： Takashi Endo , Toshio Okochi , Shunsuke Ota , Tatsuya Kameyama
发明人： Takashi Endo , Toshio Okochi , Shunsuke Ota , Tatsuya Kameyama
CPC分类号： G06F21/72 , G06F9/3017 , G06F9/30174 , G06F9/3867 , G06F21/71 , H04L9/0631 , H04L9/088 , H04L2209/125
摘要： It is possible to achieve the protection of software with reduced overhead. For example, a memory for storing an encrypted code prepared in advance and a decryptor module for decrypting the code are provided. The decryptor module includes, for example, a three-stage pipeline and a selector for selecting one output from the outputs of each stage of the pipeline. When a branch instruction is issued and subsequent inputs of the pipeline are in the order of CD′1, CD′2, . . . , the decryptor module outputs a first decrypted code by performing a one-stage pipeline process to CD′1. Next, the decryptor module outputs a second decrypted code by performing a two-stage pipeline process to CD′2, and the decryptor module outputs a third decrypted code by performing a three-stage pipeline process to CD′3 (and subsequent codes). Therefore, in particular, the overhead to CD′1 can be reduced.
摘要翻译： 可以减少开销来实现对软件的保护。 例如，提供用于存储预先准备的加密代码的存储器和用于解密代码的解密器模块。 解密器模块包括例如三级流水线和用于从流水线的每个级的输出中选择一个输出的选择器。 当发出分支指令并且管道的后续输入是CD'1，CD'2的顺序时。 。 。 解码器模块通过对CD'1执行一级流水线处理来输出第一解密码。 接下来，解码器模块通过对CD'2执行两级流水线处理来输出第二解密码，并且解密器模块通过对CD'3（和后续码）执行三级流水线处理来输出第三解密码。 因此，特别地，CD'1的开销可以降低。
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公开(公告)号：US20090232366A1
公开(公告)日：2009-09-17
申请号：US12314844
申请日：2008-12-17
申请人： Toshio Okochi , Kei Suzuki , Kazuhiko Matsumoto
发明人： Toshio Okochi , Kei Suzuki , Kazuhiko Matsumoto
CPC分类号： G06Q10/10
摘要： Provided is an information processing system which has a plurality of tags, a tag reader, a digital-pen, and a server. The plurality of tags each hold a tag identifier. The tag reader reads the tag identifier held in each of the plurality of tags. The digital-pen reads location information, which identifies a location where handwriting is made on paper. The server keeps work record including information that associates the tag identifier recorded in the server in advance with the location on paper. When it is judged that the read tag identifier and a handwriting location identified by the location information are associated with each other, the server judges whether or not the read tag identifier matches the tag identifier recorded in advance that is associated by the work record with the handwriting location identified by the location information. The server outputs a result of the judging.
摘要翻译： 提供了具有多个标签，标签读取器，数字笔和服务器的信息处理系统。 多个标签各自保存标签标识符。 标签读取器读取保存在多个标签中的每一个中的标签标识符。 数字笔读取位置信息，其标识在纸上进行手写的位置。 服务器保存工作记录，包括将服务器中记录的标签标识符与纸张上的位置预先相关联的信息。 当判断出读取的标签标识符和由位置信息识别的手写位置彼此相关联时，服务器判断读取的标签标识符是否与预先记录的与工作记录相关联的标签标识符与 由位置信息识别的手写位置。 服务器输出判断结果。
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公开(公告)号：US20070255980A1
公开(公告)日：2007-11-01
申请号：US11734361
申请日：2007-04-12
IPC分类号： G06F11/00
摘要： A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is written in a memory, and in the case when the control transits from the code block to other code block, by use of code block operation values obtained beforehand from these two code block IDs thereof, the code block ID in the memory is updated, and it is judged whether the updated code block ID in the memory and the code block ID allotted to the code block as the execution objective are identical or not so that a control flow error is detected.
摘要翻译： 要由计算机执行的程序被分成多个代码块，并且将唯一的代码块ID分配给每个代码块。 在开始执行程序的时刻，与执行开始地址相对应的代码块ID被写入存储器中，并且在控制从代码块转移到其他代码块的情况下，通过使用代码块 从这两个代码块ID预先获得的操作值被更新，存储器中的代码块ID被更新，并且判断存储器中更新的代码块ID和作为执行目标分配给代码块的代码块ID是否是 相同或不相同，从而检测到控制流量错误。
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公开(公告)号：US5426612A
公开(公告)日：1995-06-20
申请号：US115876
申请日：1993-09-01
申请人： Hiroshi Ichige , Junichi Kono , Toshio Okochi
发明人： Hiroshi Ichige , Junichi Kono , Toshio Okochi
CPC分类号： G06F5/10
摘要： The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof.Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide.In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.
摘要翻译： 以并行方式读取的数据项的位数和以并行方式写入的数据项的位数与至少2的整数相关，从而实现半导体存储器之间的数据传送效率的提高 装置及其外部。 此外，在FIFO类型的半导体存储器件中，使用写计数器和读计数器的值来计算存储的数据项的数量，从而即使读取操作也能够准确地获取存储数据项的数量 并写入数据项重合。 在具有内置地址计数器的半导体存储器件中，基于外部指令选择地址计数器的值或外部地址信号，以便寻址存储器单元，从而实现对存储器的随机存取的促进 并且还清除任何所需的存储器单元的数据项。
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9.发明授权Data communication system prioritizing data transfer over microcomputer data interrupt processing 失效数据通信系统通过微机数据中断处理优先处理数据传输
公开(公告)号：US5305441A
公开(公告)日：1994-04-19
申请号：US856555
申请日：1992-03-24
申请人： Toshio Okochi , Takeshi Miyazaki
发明人： Toshio Okochi , Takeshi Miyazaki
CPC分类号： G06F13/28
摘要： A microcomputer system comprising a central processor unit, communication apparatus having a first memory to store receipt data, data transfer controller to transfer the receipt data stored in the first memory, a second memory, and counting apparatus, wherein the receipt data consists of at least one unit information item, and the counting apparatus is caused to count up in accordance with a number of the unit information items.
摘要翻译： 一种微型计算机系统，包括中央处理器单元，具有存储收据数据的第一存储器的通信装置，用于传送存储在第一存储器中的接收数据的数据传输控制器，第二存储器和计数装置，其中，接收数据至少包括 一个单位信息项目和计数装置根据单位信息项的数量进行计数。
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公开(公告)号：US5255238A
公开(公告)日：1993-10-19
申请号：US794824
申请日：1991-11-18
申请人： Hiroshi Ichige , Junichi Kono , Toshio Okochi
发明人： Hiroshi Ichige , Junichi Kono , Toshio Okochi
CPC分类号： G06F5/10
摘要： The number of bits of data items read in parallel fashion and the number of bits of data items written in parallel fashion are related to be at least a whole number multiple of 2, thereby to achieve enhancement in the efficiency of data transfer between a semiconductor memory device and the exterior thereof.Further, in a semiconductor memory device of FIFO type, the number of stored data items is calculated using the values of a write counter and a read counter, thereby to achieve the accurate acquisition of the number of stored data items even when the operations of reading and writing data items coincide.In a semiconductor memory device having a built-in address counter, the value of the address counter or an external address signal is selected on the basis of an external instruction in order to address a memory cell, thereby to achieve facilitation of random accesses to memory cells and also the clearing of the data items of any desired memory cells.
摘要翻译： 以并行方式读取的数据项的位数和以并行方式写入的数据项的位数与至少2的整数相关，从而实现半导体存储器之间的数据传送效率的提高 装置及其外部。 此外，在FIFO类型的半导体存储器件中，使用写计数器和读计数器的值来计算存储的数据项的数量，从而即使读取操作也能够准确地获取存储数据项的数量 并写入数据项重合。 在具有内置地址计数器的半导体存储器件中，基于外部指令选择地址计数器的值或外部地址信号，以便寻址存储器单元，从而实现对存储器的随机存取的促进 并且还清除任何所需的存储器单元的数据项。
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