发明授权
US6090714A Chemical mechanical polish (CMP) planarizing trench fill method
employing composite trench fill layer
有权
化学机械抛光(CMP)平面化沟槽填充法采用复合沟槽填充层
- 专利标题: Chemical mechanical polish (CMP) planarizing trench fill method employing composite trench fill layer
- 专利标题(中): 化学机械抛光(CMP)平面化沟槽填充法采用复合沟槽填充层
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申请号: US177189申请日: 1998-10-23
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公开(公告)号: US6090714A公开(公告)日: 2000-07-18
- 发明人: Syun-Ming Jang , Chu-Yun Fu
- 申请人: Syun-Ming Jang , Chu-Yun Fu
- 申请人地址: TWX Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company
- 当前专利权人: Taiwan Semiconductor Manufacturing Company
- 当前专利权人地址: TWX Hsin-Chu
- 主分类号: H01L21/3105
- IPC分类号: H01L21/3105 ; H01L21/316 ; H01L21/762 ; H01L21/302
摘要:
A method for forming a planarized trench fill layer within a trench within a substrate. There is first provided a substrate having a trench formed therein. There is then formed over the substrate and at least partially filling the trench a first trench fill layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. There is then formed upon the first trench fill layer a second trench fill layer formed employing a subatmospheric pressure thermal chemical vapor deposition (SACVD) method employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then planarized by employing a chemical mechanical polish (CMP) planarizing method the second trench fill layer and the first trench fill layer to form a patterned planarized trench fill layer within the trench. When employing the method, the first trench fill layer is formed to a first thickness and the second trench fill layer is formed to a second thickness, where the first thickness and the second thickness are chosen such that there is attenuated erosion of the substrate when forming the patterned planarized trench fill layer within the trench while employing the chemical mechanical polish (CMP) planarizing method. The method is particularly useful for forming patterned planarized trench fill dielectric layers within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications.