发明授权
US6101627A Information processing system and logic LSI, detecting a fault in the
system or the LSI, by using internal data processed in each of them
失效
信息处理系统和逻辑LSI，通过使用它们中的每一个处理的内部数据来检测系统或LSI中的故障
- 专利标题： Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them
- 专利标题（中）： 信息处理系统和逻辑LSI，通过使用它们中的每一个处理的内部数据来检测系统或LSI中的故障
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申请号： US206153申请日： 1998-12-07
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公开(公告)号： US6101627A公开(公告)日： 2000-08-08
- 发明人: Tetsuya Shimomura , Fumio Murabayashi , Kotaro Shimamura , Nobuyasu Kanekawa , Takashi Hotta
- 申请人： Tetsuya Shimomura , Fumio Murabayashi , Kotaro Shimamura , Nobuyasu Kanekawa , Takashi Hotta
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX8-4127 19960112
- 主分类号： G06F11/16
- IPC分类号： G06F11/16 ; G06F11/18 ; G06F11/20 ; G06F11/22 ; G06F11/30 ; G06F13/00 ; G06F15/78 ; H02H3/05 ; G06F7/02 ; G06F11/08
摘要：
An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective ones result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.
公开/授权文献
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