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1.发明授权Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them 失效信息处理系统和逻辑LSI，通过使用它们中的每一个处理的内部数据来检测系统或LSI中的故障
公开(公告)号：US6101627A
公开(公告)日：2000-08-08
申请号：US206153
申请日：1998-12-07
IPC分类号： G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F11/30 , G06F13/00 , G06F15/78 , H02H3/05 , G06F7/02 , G06F11/08
CPC分类号： G06F11/1637 , G06F11/1654 , G06F11/2025 , G06F11/2038 , G06F11/2043
摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective ones result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.
摘要翻译： 信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。 每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。 每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。 故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。
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公开(公告)号：US5848238A
公开(公告)日：1998-12-08
申请号：US778685
申请日：1997-01-03
CPC分类号： G06F11/1637 , G06F11/1654 , G06F11/2025 , G06F11/2038 , G06F11/2043
摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.
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3.发明授权Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them 失效信息处理系统和逻辑LSI，通过使用它们中的每一个处理的内部数据来检测系统或LSI中的故障公开(公告)号：US06385755B1
公开(公告)日：2002-05-07
申请号：US09613276
申请日：2000-07-10
IPC分类号： G11C2900
CPC分类号： G06F11/1637 , G06F11/1654 , G06F11/2025 , G06F11/2038 , G06F11/2043
摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.
摘要翻译： 信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。 每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。 每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。 故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。
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4.发明授权
公开(公告)号：US6101596A
公开(公告)日：2000-08-08
申请号：US894924
申请日：1997-09-03
CPC分类号： G06F9/3838 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3859
摘要： An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The scale of the necessary hardware is reduced by the processor using a register conflict detector and a scoreboard. The register conflict detector detects register conflict over a period of short latency processing, and the scoreboard checks for register conflict beyond the short latency process period and into a period of long latency processing. The processor controls the issue of instructions based on the detected register conflict status.
摘要翻译： PCT No.PCT / JP95 / 00356 Sec。 371日期：1997年9月3日 102（e）日期1997年9月3日PCT Filed Mar. 6，1995 PCT Pub。 公开号WO96 / 27833 日期1996年9月12日信息处理器能够消除短延时和长延迟过程中的寄存器冲突，并通过有效使用寄存器实现高速流水线处理。 处理器使用寄存器冲突检测器和记分板来减少所需硬件的规模。 寄存器冲突检测器在短时延处理期间检测寄存器冲突，并且记分板检查超出短延迟处理周期的寄存器冲突并进入长延迟处理期间。 处理器根据检测到的寄存器冲突状态控制指令的问题。
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公开(公告)号：US06437621B2
公开(公告)日：2002-08-20
申请号：US09816100
申请日：2001-03-26
申请人： Kazuo Kato , Takashi Sase , Takashi Hotta , Fumio Murabayashi
发明人： Kazuo Kato , Takashi Sase , Takashi Hotta , Fumio Murabayashi
IPC分类号： H03K317
CPC分类号： C08K5/5419 , C08G77/442 , C08G77/50 , C08L27/12 , C08L69/00
摘要： A waveform shaping circuit is provided so that the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency. An inverter which receives the clock pulses through an alternating current coupling capacitor is provided with a non-linear limiter element for limiting an amplitude of an output symmetrically on positive and negative sides thereof. A first current-limiting impedance and a second current-limiting impedance are connected between a power supply side terminal of the inverter and a power supply bus and between a grounding side terminal of the inverter and a grounding bus, respectively.
摘要翻译： 提供波形整形电路，使得即使时钟脉冲是低电压和高频率，时钟脉冲的占空因数也可以高精度地设置为50％。 通过交流耦合电容器接收时钟脉冲的逆变器设置有非线性限制器元件，用于在其正侧和负侧对称地限制输出的幅度。 逆变器的电源侧端子与电源总线之间以及逆变器的接地侧端子与接地母线之间分别连接有第一限流阻抗和第二限流阻抗。
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6.发明授权
公开(公告)号：US5684729A
公开(公告)日：1997-11-04
申请号：US530471
申请日：1995-09-19
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49947 , G06F7/49994
摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.
摘要翻译： 为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量， 点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果， 移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。
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7.发明授权Current-driven signal interface implemented in semiconductor integrated circuit device 失效电流驱动信号接口在半导体集成电路器件中实现
公开(公告)号：US5363332A
公开(公告)日：1994-11-08
申请号：US860442
申请日：1992-03-30
IPC分类号： H03K19/013 , H03K19/0175 , H03K19/018 , G11C8/00 , H01L27/06
CPC分类号： H03K19/013 , H03K19/017518 , H03K19/01806
摘要： A semiconductor integrated circuit device is arranged to have a plurality of logic circuit blocks, a data signal path for interconnecting logic circuit blocks and for providing a function of interfacing a current-driven signal. The logic circuit block on a signal output side includes an output circuit connected to the data signal path and a switching element formed of an NMOS transistor for controlling current flowing through the data signal path in response to an input signal applied to an input terminal of the output circuit. The logic circuit block on a signal input side includes an input circuit connected to the data signal path. The input circuit includes a bipolar transistor having an emitter connected to a constant current source, a collector forming an output terminal, and a base set at a fixed potential. The data signal path led from the output circuit is connected to the emitter of the bipolar transistor. The arrangement results in reducing a signal amplitude on the signal bus, thereby speeding up the transmission of the data signal and reducing noise of the signal.
摘要翻译： 半导体集成电路器件被布置为具有多个逻辑电路块，用于互连逻辑电路块的数据信号路径，并且用于提供与电流驱动信号接口的功能。 信号输出侧的逻辑电路块包括连接到数据信号路径的输出电路和由NMOS晶体管形成的开关元件，用于响应于施加到数据信号路径的输入端子的输入信号来控制流过数据信号路径的电流 输出电路。 信号输入侧的逻辑电路块包括连接到数据信号路径的输入电路。 输入电路包括具有连接到恒流源的发射极，形成输出端的集电极和固定电位的基极的双极晶体管。 从输出电路引出的数据信号路径连接到双极晶体管的发射极。 该结构可以减少信号总线上的信号幅度，从而加速数据信号的传输并降低信号的噪声。
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公开(公告)号：US5841300A
公开(公告)日：1998-11-24
申请号：US838193
申请日：1997-04-16
IPC分类号： H03K19/003 , H03K19/096
CPC分类号： H03K19/00338
摘要： The present invention is intended to provide a conventional circuit apparatus which is highly tolerant to noises and operates at a higher speed than a completely complementary static CMOS circuit. To achieve this, circuit apparatus according to the present invention is provided with a plurality of CMOS static logic circuits which are series-connected and potential setting means which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore circuit operation is speeded up and .alpha. particle noise and noises due to charge redistribution effect or leakage current can be prevented.
摘要翻译： 本发明旨在提供一种传统的电路设备，其高度耐受噪声并且以比完全互补的静态CMOS电路更高的速度工作。 为了实现这一点，根据本发明的电路装置设置有多个串联的CMOS静态逻辑电路和电位设置装置，其连接到这些逻辑电路的输出部分并将输出部分的输出设置为 与时钟信号同步的低电平，从而通过NMOS电路的操作来传播信号。 换句话说，信号传播延迟仅在N型逻辑块导通时才发生。 因此，电路操作加快，可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。
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公开(公告)号：US06590425B2
公开(公告)日：2003-07-08
申请号：US09887065
申请日：2001-06-25
IPC分类号： H03K19096
CPC分类号： H03K19/00338
摘要： There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented. There is also disclosed a parallel data processing apparatus which features such logic circuitry, the data processing apparatus having both a plurality of data processing units, each having a processor and a memory, and a plurality of hard disks.
摘要翻译： 公开了一种电路装置，其高度耐受噪声并以比传统的完全互补的静态CMOS电路更高的速度工作。 为了实现这一点，电路装置具有串联连接的多个CMOS静态逻辑电路和连接到这些逻辑电路的输出部分的电位设置电路，并将输出部分的输出与 时钟信号，从而通过NMOS电路的操作传播信号。 换句话说，信号传播延迟仅在N型逻辑块导通时才发生。 因此，可以防止电路操作加剧，并且可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。 还公开了一种具有这种逻辑电路的并行数据处理装置，数据处理装置具有多个数据处理单元，每个数据处理单元具有处理器和存储器，以及多个硬盘。
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公开(公告)号：US5539686A
公开(公告)日：1996-07-23
申请号：US315591
申请日：1994-09-30
IPC分类号： H03K19/013 , H03K19/0175 , H03K19/018 , G06F7/50
CPC分类号： H03K19/013 , H03K19/017518 , H03K19/01806
摘要： A carry propagating device, provided on a single substrate, is constituted by groups of first and second MOS transistors, a third MOS transistor, a bipolar transistor and first and second impedance elements. An output of the carry propagating device is provided at the collector of the bipolar transistor and is connected to a first power supply terminal through the first impedance element, the emitter is connected to a second power supply terminal through the second impedance element, and the base is connected to a fixed potential source. The first MOS transistors are connected in series between the emitter of the bipolar transistor and the second power supply terminal through the third MOS transistor controlled by a carry signal. As to the second MOS transistors, one is connected in parallel to the second impedance element and each of the remaining ones is connected between a common connection of a respective pair of adjacent ones of the series-connected first MOS transistors and the second power supply terminal. There is thus effected a speed-up of the carry signal and thereby a speeding-up of the signal processing. There is also provided a wiring scheme for preventing noise interference between different wirings. Moreover, a device has been schemed for a plurality of logic circuit blocks and including a data signal path for interconnecting different logic circuit blocks and facilitating the interfacing of a current-driven signal.
摘要翻译： 设置在单个基板上的携带传播装置由第一和第二MOS晶体管，第三MOS晶体管，双极晶体管和第一和第二阻抗元件组构成。 进位传播装置的输出设置在双极晶体管的集电极处，并通过第一阻抗元件连接到第一电源端子，发射极通过第二阻抗元件连接到第二电源端子，基极 连接到固定电位源。 第一MOS晶体管通过由进位信号控制的第三MOS晶体管串联连接在双极晶体管的发射极和第二电源端子之间。 对于第二MOS晶体管，一个与第二阻抗元件并联连接，其余的每个连接在一对相邻的串联连接的第一MOS晶体管和第二电源端子的公共连接 。 因此，进行了进位信号的加速，从而加速了信号处理。 还提供了用于防止不同布线之间的噪声干扰的布线方案。 此外，已经针对多个逻辑电路块设计了一种器件，并且包括用于互连不同逻辑电路块的数据信号路径，并且有助于电流驱动信号的接口。
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