Invention Grant
US6107149A CMOS semiconductor device comprising graded junctions with reduced
junction capacitance
有权
CMOS半导体器件包括具有减小的结电容的分级结
- Patent Title: CMOS semiconductor device comprising graded junctions with reduced junction capacitance
- Patent Title (中): CMOS半导体器件包括具有减小的结电容的分级结
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Application No.: US325628Application Date: 1999-06-04
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Publication No.: US6107149APublication Date: 2000-08-22
- Inventor: David Wu , Scott Luning
- Applicant: David Wu , Scott Luning
- Applicant Address: CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: CA Sunnyvale
- Main IPC: H01L21/265
- IPC: H01L21/265 ; H01L21/336 ; H01L27/092 ; H01L29/78
Abstract:
A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.
Public/Granted literature
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