公开(公告)号：US6107149A

公开(公告)日：2000-08-22

申请号：US325628

申请日：1999-06-04

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

Abstract translation: 形成具有N沟道晶体管的CMOS半导体器件，其包括具有减小的结电容的梯度结。 通过在源极/漏极注入之后在栅电极上形成第二侧壁间隔物并且将具有高扩散率的N型杂质（例如P）离子注入到A5植入物中，然后进行活化退火来实现渐变结。

公开(公告)号：US06949436B2

公开(公告)日：2005-09-27

申请号：US10824428

申请日：2004-04-15

Applicant: James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

Inventor： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

Abstract translation: 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物下形成复合氧化物/氮化物衬垫来制造。 实施例包括通过解耦等离子体沉积沉积保形氧化物层，通过去耦等离子体沉积沉积共形氮化物层，沉积间隔层然后蚀刻。

公开(公告)号：US06482726B1

公开(公告)日：2002-11-19

申请号：US09690152

申请日：2000-10-17

Applicant: Massud Aminpur ,  David Wu ,  Scott Luning

Inventor： Massud Aminpur ,  David Wu ,  Scott Luning

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.

Abstract translation: 提供了一种方法，该方法包括在衬底层上方形成栅介质层，在栅极介电层上方形成栅极导体层，在栅极导体层之上形成第一硬掩模层，并形成第二硬掩模层 第一硬掩模层。 该方法还包括在第二硬掩模层之上形成修整的光致抗蚀剂掩模，并且在第二硬掩模层中使用经修剪的光致抗蚀剂掩模形成图案化的硬掩模以去除第二硬掩模层的部分，图案化硬掩模具有第一 尺寸。 该方法还包括通过去除与图案化的硬掩模相邻的第一硬掩模层的部分来形成第一硬掩模层中的选择性蚀刻的硬掩模，该选择性蚀刻的硬掩模具有小于第一尺寸的第二尺寸，以及形成栅极 结构，其使用选择性蚀刻的硬掩模以去除栅极介电层上方的栅极导体层的部分。

公开(公告)号：US06351013B1

公开(公告)日：2002-02-26

申请号：US09352339

申请日：1999-07-13

Applicant: Scott Luning ,  David Wu ,  Khanh Tran

Inventor： Scott Luning ,  David Wu ,  Khanh Tran

IPC: H01L31062

CPC classification number: H01L29/6659 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66598 ,  Y10S257/90

Abstract: The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Abstract translation: 通过在源极/漏极区域之上的栅电极的角部形成低介电常数（K）材料的子间隔物来减小半导体器件的栅电极和源/漏区之间的电容。 随后，在子间隔物之上形成绝缘侧壁间隔物以屏蔽浅源/漏区，从而避免随后的杂质注入。 所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。

公开(公告)号：US6114210A

公开(公告)日：2000-09-05

申请号：US979364

申请日：1997-11-26

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a drain region with a graded N-LDD junction. The graded N-LDD junction is obtained by plural ion implantations at different implantation dosages, energies and angles. The graded N-LDD junction reduces the electric field around the drain, thereby increasing the HCI lifetime without adversely impacting the short channel effect.

Abstract translation: 形成具有N沟道晶体管的CMOS半导体器件，N沟道晶体管包括具有渐变N-LDD结的漏极区。 通过以不同植入剂量，能量和角度的多个离子注入获得分级N-LDD结。 分级N-LDD结降低了漏极周围的电场，从而提高了HCl寿命，而不会对短沟道效应产生不利影响。

公开(公告)号：US5952693A

公开(公告)日：1999-09-14

申请号：US923996

申请日：1997-09-05

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

公开(公告)号：US08329519B2

公开(公告)日：2012-12-11

申请号：US13305449

申请日：2011-11-28

Applicant: Zhonghai Shi ,  David Wu ,  Mark Michael ,  Donna Michael, legal representative

Inventor： Zhonghai Shi ,  David Wu ,  Mark Michael

IPC: H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Abstract translation: 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US07704320B2

公开(公告)日：2010-04-27

申请号：US10838908

申请日：2004-05-03

Applicant: David W. M. Marr ,  Tieying Gong ,  David Wu

Inventor： David W. M. Marr ,  Tieying Gong ,  David Wu

IPC: C30B30/04

CPC classification number: C30B7/00 ,  C30B29/54

Abstract: The methods provided use external fields such as light and electricity as a means of directing the crystallization of concentrated colloidal systems. Not only can nucleation be directed, crystal melting can be carefully controlled and light-induced crystal diffraction used as a means of directing light propagation. A number of factors play a significant role on the crystallization rate and location, including the intensity of the light field, the magnitude of the electric field, the colloid concentration, the colloid size, and the colloid composition. In varying these parameters, kinetics in these processes are extremely fast when compared to traditional colloidal crystallization approaches.

Abstract translation: 提供的方法使用诸如光和电的外部领域作为指导浓缩胶体体系的结晶的手段。 成核不仅可以引导，晶体熔化也可以小心控制，光诱导的晶体衍射用作引导光传播的手段。 许多因素对结晶速率和位置都起着重要的作用，包括光场强度，电场强度，胶体浓度，胶体尺寸和胶体组成。 在改变这些参数时，与传统的胶体结晶方法相比，这些方法中的动力学非常快。

公开(公告)号：US20080165199A1

公开(公告)日：2008-07-10

申请号：US11621917

申请日：2007-01-10

Applicant: Jian Wei ,  James M. Brown ,  David Wu

Inventor： Jian Wei ,  James M. Brown ,  David Wu

IPC: G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20

Abstract: A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.

Abstract translation: 一种设备具有用于处理三维（3D）图形流水线的顶点处理阶段，子屏幕划分阶段和像素渲染阶段的处理器。 该处理器包括处理线程，其平衡3D图形流水线的工作负载，通过对像素渲染阶段的处理优先于其他阶段。 并行和独立运行的每个处理线程检查子屏幕任务的任务列表中的任务级别。 如果该级别低于阈值，则清空或子屏幕任务都被锁定，则处理线程循环到顶点处理阶段。 否则，处理线程在像素渲染阶段处理子屏幕任务。

公开(公告)号：US20070021217A1

公开(公告)日：2007-01-25

申请号：US11183795

申请日：2005-07-19

Applicant: David Wu

Inventor： David Wu

IPC: A63F9/24

CPC classification number: G07F17/32 ,  G07F17/3216 ,  G07F17/3227

Abstract: An advertising decorative and protecting structure for a base of a game machine, the structure has a base provided therein with a cash box, the base is provided on its top surface with members such as a display screen and a top light box as the components of the main body of the game machine; the base is provided beneath the top and on the rear of the front face thereof with a liftable transparent door plate; this liftable transparent door plate is assembled on the rear of it at least with an integrally formed illumination device, so that it can generate an illumination function by which light is penetrable to the outside during operating the game machine, and also can form a covering and protecting structure for the entire base. The structure can elevate the effect of decoration of the base of the game machine in order to attract consumers, and further to enhance the function of protection of the cash box.

Abstract translation: 一种用于游戏机基座的广告装饰和保护结构，该结构在其中设置有一个现金箱，底座在其顶表面上设置有诸如显示屏和顶灯箱的部件作为 游戏机的主体; 底座在其正面的顶部和后部设置有可升降的透明门板; 该可升降透明门板至少具有一体形成的照明装置，组装在其后部，从而能够在操作游戏机时产生光线可透过外部的照明功能，也可以形成遮盖物 保护整个基地的结构。 结构可以提升游戏机底座的装饰效果，吸引消费者，进一步提升保护箱的功能。