公开(公告)号：US6107149A

公开(公告)日：2000-08-22

申请号：US325628

申请日：1999-06-04

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

Abstract translation: 形成具有N沟道晶体管的CMOS半导体器件，其包括具有减小的结电容的梯度结。 通过在源极/漏极注入之后在栅电极上形成第二侧壁间隔物并且将具有高扩散率的N型杂质（例如P）离子注入到A5植入物中，然后进行活化退火来实现渐变结。

公开(公告)号：US06949436B2

公开(公告)日：2005-09-27

申请号：US10824428

申请日：2004-04-15

Applicant: James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

Inventor： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

Abstract translation: 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物下形成复合氧化物/氮化物衬垫来制造。 实施例包括通过解耦等离子体沉积沉积保形氧化物层，通过去耦等离子体沉积沉积共形氮化物层，沉积间隔层然后蚀刻。

公开(公告)号：US06482726B1

公开(公告)日：2002-11-19

申请号：US09690152

申请日：2000-10-17

Applicant: Massud Aminpur ,  David Wu ,  Scott Luning

Inventor： Massud Aminpur ,  David Wu ,  Scott Luning

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.

Abstract translation: 提供了一种方法，该方法包括在衬底层上方形成栅介质层，在栅极介电层上方形成栅极导体层，在栅极导体层之上形成第一硬掩模层，并形成第二硬掩模层 第一硬掩模层。 该方法还包括在第二硬掩模层之上形成修整的光致抗蚀剂掩模，并且在第二硬掩模层中使用经修剪的光致抗蚀剂掩模形成图案化的硬掩模以去除第二硬掩模层的部分，图案化硬掩模具有第一 尺寸。 该方法还包括通过去除与图案化的硬掩模相邻的第一硬掩模层的部分来形成第一硬掩模层中的选择性蚀刻的硬掩模，该选择性蚀刻的硬掩模具有小于第一尺寸的第二尺寸，以及形成栅极 结构，其使用选择性蚀刻的硬掩模以去除栅极介电层上方的栅极导体层的部分。

公开(公告)号：US06351013B1

公开(公告)日：2002-02-26

申请号：US09352339

申请日：1999-07-13

Applicant: Scott Luning ,  David Wu ,  Khanh Tran

Inventor： Scott Luning ,  David Wu ,  Khanh Tran

IPC: H01L31062

CPC classification number: H01L29/6659 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66598 ,  Y10S257/90

Abstract: The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Abstract translation: 通过在源极/漏极区域之上的栅电极的角部形成低介电常数（K）材料的子间隔物来减小半导体器件的栅电极和源/漏区之间的电容。 随后，在子间隔物之上形成绝缘侧壁间隔物以屏蔽浅源/漏区，从而避免随后的杂质注入。 所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。

公开(公告)号：US6114210A

公开(公告)日：2000-09-05

申请号：US979364

申请日：1997-11-26

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a drain region with a graded N-LDD junction. The graded N-LDD junction is obtained by plural ion implantations at different implantation dosages, energies and angles. The graded N-LDD junction reduces the electric field around the drain, thereby increasing the HCI lifetime without adversely impacting the short channel effect.

Abstract translation: 形成具有N沟道晶体管的CMOS半导体器件，N沟道晶体管包括具有渐变N-LDD结的漏极区。 通过以不同植入剂量，能量和角度的多个离子注入获得分级N-LDD结。 分级N-LDD结降低了漏极周围的电场，从而提高了HCl寿命，而不会对短沟道效应产生不利影响。

公开(公告)号：US5952693A

公开(公告)日：1999-09-14

申请号：US923996

申请日：1997-09-05

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

公开(公告)号：US08193592B2

公开(公告)日：2012-06-05

申请号：US12904662

申请日：2010-10-14

Applicant: Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

Inventor： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

Abstract translation: 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US08148214B2

公开(公告)日：2012-04-03

申请号：US12360961

申请日：2009-01-28

Applicant: Andrew M. Waite ,  Scott Luning

Inventor： Andrew M. Waite ,  Scott Luning

IPC: H01L21/00

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

Abstract translation: 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US20110062498A1

公开(公告)日：2011-03-17

申请号：US12561685

申请日：2009-09-17

Applicant: Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

Inventor： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

Abstract translation: 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

公开(公告)号：US07893493B2

公开(公告)日：2011-02-22

申请号：US11456326

申请日：2006-07-10

Applicant: Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

Inventor： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC: H01L27/12 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

Abstract: An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

Abstract translation: 中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中 衬垫，其中外延生长的硅基本上是无层错的。