发明授权
US6114887A Apparatus for generating bus clock signals with a 1/N characteristic in
a 2/N mode clocking scheme
失效
用于以2 / N模式计时方案产生具有1 / N特性的总线时钟信号的装置
- 专利标题： Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
- 专利标题（中）： 用于以2 / N模式计时方案产生具有1 / N特性的总线时钟信号的装置
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申请号： US971939申请日： 1997-11-17
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公开(公告)号： US6114887A公开(公告)日： 2000-09-05
- 发明人: Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
- 申请人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： G06F1/12
- IPC分类号： G06F1/12 ; H03K1/04
摘要：
A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
公开/授权文献
- US5367252A Test fixture for electronic circuit boards 公开/授权日：1994-11-22
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