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公开(公告)号：US07336115B2
公开(公告)日：2008-02-26
申请号：US11350149
申请日：2006-02-08
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /或前一个子树。
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公开(公告)号：US06975154B1
公开(公告)日：2005-12-13
申请号：US10426473
申请日：2003-04-29
申请人： Bruce Pedersen
发明人： Bruce Pedersen
摘要： An exemplary reduced-power-consumption network includes a frequency divider coupled through global clock lines to a plurality of double-edge triggered registers. Another exemplary network includes a plurality of individually programmable frequency dividers coupled through local clock lines to a plurality of double-edge triggered registers.
摘要翻译： 示例性的降低功耗网络包括通过全局时钟线耦合到多个双边缘触发寄存器的分频器。 另一示例性网络包括通过本地时钟线耦合到多个双边缘触发寄存器的多个单独可编程分频器。
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公开(公告)号：US6104219A
公开(公告)日：2000-08-15
申请号：US170818
申请日：1998-10-13
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。 时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。
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公开(公告)号：US6084441A
公开(公告)日：2000-07-04
申请号：US900279
申请日：1997-07-25
申请人： Shuichi Kawai
发明人： Shuichi Kawai
CPC分类号： G06F1/14
摘要： A data processing apparatus functions as a timer or counter by counting clock pulses of a system clock signal to generate a timing signal. The system clock signal is generated as one of either a first or a second basic clock signal generated by two respective oscillators. Even if the second basic clock signal which has a lower frequency fluctuates, the data processing apparatus can accurately generate a pulse signal having a desired period. When the first basic clock signal is selected as the system clock signal, the second basic clock signal is measured with the system clock signal. When the second basic clock signal is selected as the system clock signal, a numerical value up to which the clock pulses of the system clock signal are counted is corrected on the basis of the measured second basic clock signal.
摘要翻译： 数据处理装置通过对系统时钟信号的时钟脉冲进行计数来产生定时信号作为定时器或计数器。 系统时钟信号被生成为由两个相应振荡器产生的第一或第二基本时钟信号之一。 即使具有较低频率的第二基本时钟信号波动，数据处理装置也可以精确地产生具有期望周期的脉冲信号。 当选择第一个基本时钟信号作为系统时钟信号时，用系统时钟信号测量第二个基本时钟信号。 当选择第二基本时钟信号作为系统时钟信号时，基于所测量的第二基本时钟信号来校正对系统时钟信号的时钟脉冲进行计数的数值。
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公开(公告)号：US6069514A
公开(公告)日：2000-05-30
申请号：US65643
申请日：1998-04-23
申请人： Scott M. Fairbanks
发明人： Scott M. Fairbanks
CPC分类号： G06F1/10 , H03K3/0315 , H03K3/86 , H03L7/00
摘要： A system for distributing clock signals to multiple locations on a chip with minimal skew is disclosed. A series of FIFO control structures, connected in a ring by signal lines of substantially equal length, generates multiple clock signals of equal phase and frequency. The oscillation frequency of the FIFO control ring may be increased to accommodate higher-speed chips, while maintaining synchronization of clock pulses at each stage of the FIFO control ring.
摘要翻译： 公开了一种用于以最小的偏斜将时钟信号分配到芯片上的多个位置的系统。 通过基本上相等长度的信号线在环中连接的一系列FIFO控制结构产生相等和频率相等的多个时钟信号。 可以增加FIFO控制环的振荡频率以适应较高速度的芯片，同时保持FIFO控制环的每一级的时钟脉冲的同步。
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6.发明授权Method and apparatus for distributing a clock on the silicon backside of an integrated circuit 失效用于在集成电路的硅背面上分配时钟的方法和装置
公开(公告)号：US6037822A
公开(公告)日：2000-03-14
申请号：US938486
申请日：1997-09-30
IPC分类号： H01L23/48 , H01L23/522 , H03K1/04
CPC分类号： H01L23/522 , H01L23/481 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01079 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15312 , H01L2924/1532 , H01L2924/30107 , H01L2924/3011
摘要： A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.
摘要翻译： 一种用于对集成电路进行计时的方法和装置。 该装置包括集成电路，其具有设置在半导体衬底的第一侧中的时钟驱动器，以及时钟分配网络，其耦合到时钟驱动器并且设置在半导体衬底的第二侧，以发送时钟信号以使时钟信号为 集成电路。
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公开(公告)号：US5939919A
公开(公告)日：1999-08-17
申请号：US901594
申请日：1997-07-28
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
CPC分类号： G06F1/10 , H03K5/00006
摘要： A clocking scheme is provided which uses an external clock signal having a frequency F, and generates an internal master clock signal equal having a frequency lower than (e.g., 1/2) F. The internal master clock signal operating at, for example, half the speed of the external clock is routed throughout a device to components on the device requiring a clock signal (e.g., input or output buffers in a synchronous memory product). A stream of narrow pulses corresponding to rising and falling edges of the internal master clock signal are locally generated for those components which require a clock signal at full frequency. This stream of narrow pulses has a frequency of F.
摘要翻译： 提供了一种使用具有频率F的外部时钟信号的时钟方案，并产生等于具有低于（例如+ E，fra 1/2 + EE）F的频率的内部主时钟信号。内部主时钟信号操作 例如，外部时钟的一半速度通过整个设备被路由到需要时钟信号的设备上的组件（例如，同步存储器产品中的输入或输出缓冲器）。 与内部主时钟信号的上升沿和下降沿对应的窄脉冲流局部地产生于需要全频率时钟信号的那些部件。 这个窄脉冲流的频率为F.
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公开(公告)号：US5712585A
公开(公告)日：1998-01-27
申请号：US580914
申请日：1995-12-29
申请人： Deog-Kyoon Jeong
发明人： Deog-Kyoon Jeong
IPC分类号： H04L5/22 , H03K19/0185 , H03L7/089 , H03L7/099 , H03M9/00 , H04J3/04 , H04L5/14 , H04L7/00 , H04L7/033 , H04L13/10 , H04L25/02 , H04L25/08 , H04L29/10 , H03K1/04
CPC分类号： H04L7/0338 , H03K19/018592 , H03L7/0996 , H03M9/00 , H04J3/047 , H04L25/0272 , H04L25/085 , H04L5/1423 , H04L7/0337 , H03L7/0891 , H03L7/0895 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L7/0008
摘要： A system for convening between parallel data and serial data is described. In the system (b 10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is convened into serial data.
摘要翻译： 描述用于在并行数据和串行数据之间进行转换的系统。 在系统（b 10）中，并行数据（12）的各个比特被锁存到各个寄存器（117）中。 每个寄存器（117）耦合到相应的与门（110），其也连接以接收相位时钟信号。 与门（110）的输出端子连接到或门（115）。 使用系统，使用适当的相位时钟，并行数据被调入串行数据。
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公开(公告)号：US5675282A
公开(公告)日：1997-10-07
申请号：US512994
申请日：1995-08-09
申请人： Akitoshi Saito
发明人： Akitoshi Saito
CPC分类号： G06F11/0757 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , Y02B60/1217 , Y02B60/1221 , Y02B60/1282 , Y02B60/32
摘要： An integrated circuit has a plurality of circuit elements, each of which is equipped with a power saving device for conserving power. This offers design flexibility to more easily change the number of circuit elements in the integrated circuit. Each circuit element detects the input data with the aid of an input detector circuit. The input detector triggers a timer circuit to measure the time required for the circuit element to process the data. The timer circuit turns on an action flag at the start of the process, and turns off the action flag at the end of the process. When the action flag is on, a switch circuit provides either a clock signal or the power to a main circuit. This allows the main circuit to enter an activation mode. When the action flag is off, the switch circuit either provides a low-speed clock signal or suspends the supply of the clock signal or the power to the main circuit. This allows the main circuit to enter a sleep mode.
摘要翻译： 集成电路具有多个电路元件，每个电路元件配备有用于节省功率的节电装置。 这提供了设计灵活性，以更容易地改变集成电路中的电路元件的数量。 每个电路元件借助于输入检测器电路来检测输入数据。 输入检测器触发定时器电路以测量电路元件处理数据所需的时间。 定时器电路在处理开始时打开动作标志，并在处理结束时关闭动作标志。 当动作标志打开时，开关电路为主电路提供时钟信号或电源。 这允许主电路进入激活模式。 当动作标志关闭时，开关电路提供低速时钟信号或暂停提供时钟信号或向主电路供电。 这允许主电路进入睡眠模式。
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公开(公告)号：US6020774A
公开(公告)日：2000-02-01
申请号：US121296
申请日：1998-07-23
申请人： You-Ming Chiu , Jiin Lai
发明人： You-Ming Chiu , Jiin Lai
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62
摘要： A gated clock tree synthesis (CTS) method is provided for the purpose of synthesizing a gate array logic circuit to allow optimal topological arrangement of the gate array on the logic circuit. This in turn allows the logic circuit to operate more efficiently. The logic circuit includes at least one clock generator, a plurality of control gates each having one input end connected to a control signal and the other input end connected to receive the output clock signal from the clock generator, a plurality of first logic elements that are directly driven by the output clock signal from the clock generator, and a plurality of second logic elements that are driven by the gated clock signal outputted from each of the control gates under control by the control signal. The gated CTS method comprises the steps of grouping the first logic elements into a plurality of groups, connecting each group of the first logic elements via a first buffer to one of the control gates, connecting each of the second logic elements via a second buffer to the clock generator, and connecting one input end of each of the control gates to the clock generator.
摘要翻译： 提供门控时钟树合成（CTS）方法用于合成门阵列逻辑电路以允许逻辑电路上的门阵列的最佳拓扑排列。 这又允许逻辑电路更有效地操作。 逻辑电路包括至少一个时钟发生器，多个控制栅极，每个控制栅极具有一个连接到控制信号的输入端，另一个输入端连接以从时钟发生器接收输出时钟信号;多个第一逻辑元件， 由来自时钟发生器的输出时钟信号直接驱动，以及多个第二逻辑元件，其由控制信号控制的每个控制门输出的门控时钟信号驱动。 门控CTS方法包括以下步骤：将第一逻辑元件分组成多个组，将每组第一逻辑元件经由第一缓冲器连接到控制门之一，将第二逻辑元件经由第二缓冲器连接到 时钟发生器，并且将每个控制门的一个输入端连接到时钟发生器。
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