发明授权
US6121100A Method of fabricating a MOS transistor with a raised source/drain
extension
失效
制造具有升高的源极/漏极延伸的MOS晶体管的方法
- 专利标题： Method of fabricating a MOS transistor with a raised source/drain extension
- 专利标题（中）： 制造具有升高的源极/漏极延伸的MOS晶体管的方法
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申请号： US1337申请日： 1997-12-31
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公开(公告)号： US6121100A公开(公告)日： 2000-09-19
- 发明人: Ebrahim Andideh , Lawrence Brigham , Robert S. Chau , Tahir Ghani , Chia-Hong Jan , Justin Sandford , Mitchell C. Taylor
- 申请人： Ebrahim Andideh , Lawrence Brigham , Robert S. Chau , Tahir Ghani , Chia-Hong Jan , Justin Sandford , Mitchell C. Taylor
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： H01L21/225
- IPC分类号： H01L21/225 ; H01L21/336 ; H01L21/8238 ; H01L29/417 ; H01L29/45 ; H01L29/49 ; H01L29/78
摘要：
A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.
公开/授权文献
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