利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

428 条记录 (耗时 0.04 秒)

    Transistor with minimal junction capacitance and method of fabrication
    5.
    发明授权
    Transistor with minimal junction capacitance and method of fabrication 失效
    具有最小结电容的晶体管和制造方法

    公开(公告)号：US06198142B1

    公开(公告)日：2001-03-06

    申请号：US09127349

    申请日：1998-07-31

    申请人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

    发明人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

    IPC分类号： H01L2976

    CPC分类号： H01L29/66636 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/7834

    摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.

    摘要翻译： 在该制造方法中具有最小结电容的新型MOS晶体管。 根据本发明，在半导体衬底的第一表面上形成栅介质层。 然后在栅极电介质层上形成栅电极。 接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。 然后在每个凹部的表面上形成介电层。 然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

    Semiconductor transistor having a stressed channel
    7.
    发明申请
    Semiconductor transistor having a stressed channel 审中-公开
    具有应力通道的半导体晶体管

    公开(公告)号：US20100102356A1

    公开(公告)日：2010-04-29

    申请号：US12655329

    申请日：2009-12-29

    申请人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

    发明人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

    摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

    摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IDSAT和IDLIN。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

    SEMICONDUCTOR TRANSISTOR HAVING A STRESSED CHANNEL
    8.
    发明申请
    SEMICONDUCTOR TRANSISTOR HAVING A STRESSED CHANNEL 审中-公开
    具有应力通道的半导体晶体管

    公开(公告)号：US20090065808A1

    公开(公告)日：2009-03-12

    申请号：US12269829

    申请日：2008-11-12

    申请人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

    发明人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

    IPC分类号： H01L29/778

    CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

    摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

    摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IDSAT和IDLIN。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

    Semiconductor transistor having a stressed channel
    9.
    发明授权
    Semiconductor transistor having a stressed channel 有权
    具有应力通道的半导体晶体管

    公开(公告)号：US07492017B2

    公开(公告)日：2009-02-17

    申请号：US11233854

    申请日：2005-09-09

    申请人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani

    发明人： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani

    IPC分类号： H01L21/20

    CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

    摘要： A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

    摘要翻译： 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IDSAT和IDLIN。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。