发明授权
US6153928A Substrate for semiconductor package, fabrication method thereof, and
stacked-type semiconductor package using the substrate
失效
用于半导体封装的衬底,其制造方法和使用该衬底的层叠型半导体封装
- 专利标题: Substrate for semiconductor package, fabrication method thereof, and stacked-type semiconductor package using the substrate
- 专利标题(中): 用于半导体封装的衬底,其制造方法和使用该衬底的层叠型半导体封装
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申请号: US857462申请日: 1997-05-16
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公开(公告)号: US6153928A公开(公告)日: 2000-11-28
- 发明人: Jae Won Cho
- 申请人: Jae Won Cho
- 申请人地址: KRX Kyoungki-do
- 专利权人: Hyuandai Electronics Industries Co., Ltd.
- 当前专利权人: Hyuandai Electronics Industries Co., Ltd.
- 当前专利权人地址: KRX Kyoungki-do
- 优先权: KRX96/16646 19960517
- 主分类号: H01L23/12
- IPC分类号: H01L23/12 ; H01L23/13 ; H01L23/28 ; H01L23/498 ; H01L25/065 ; H01L25/07 ; H01L25/10 ; H01L25/18 ; H01L23/02
摘要:
A substrate for a semiconductor package, a fabrication method for the substrate, thereof and a stacked-type semiconductor package using the substrate, and a method of making the package are disclosed. The substrate includes: an insulator having top and bottom surfaces, there being upper and lower recesses respectively formed in the top and bottom surfaces of the insulator; plural first upper and lower conductive lines respectively formed at least in part on exposed surface of the upper and lower recesses; and plural second upper and lower conductive lines respectively formed at least in part on the top and bottom surfaces and connected with corresponding ones of the first upper and lower conductive lines, respectively, the second upper and lower conductive lines extending outwardly from the upper and lower recesses, respectively.
公开/授权文献
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