A symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output. If the clamped video level drops suddenly, a delayed version of the fixed composite sync output clocks a flip flop, creating a fault signal which discharges a memory capacitor over a time period. When composite sync pulses are again sliced, the output from the first comparator resets the flip flop. The circuit also includes a video signal detector which enables its sync outputs only when it receives a predetermined number of valid lines of video with the frequency of the lines being in a predetermined range and with the last several lines being relatively free of noise. A timer prevents muting of the outputs if the input signal frequency is disturbed only momentarily.