公开(公告)号：US5432559A

公开(公告)日：1995-07-11

申请号：US149258

申请日：1993-11-09

申请人： Bryan Bruins ,  Paul Moore

发明人： Bryan Bruins ,  Paul Moore

IPC分类号： H04N5/08 ,  H04N5/10

CPC分类号： H04N5/08

摘要： A self-adjusting window circuit suitable for fabrication as a monolithic integrated circuit. The self-adjusting window circuit comprises an input port, a positive edge detector coupled to the input port, a latch coupled to the output of the edge detector and a charging stage coupled to the latch. The input signal comprises a signal having a sequence of pulses appearing at a predetermined scan rate, for example, a composite video signal. The input port feeds the input signal to the edge detector which produces a pulse output signal in response to detecting a pulse in the input signal. The pulse output from the edge detector is latched and used to generate a charging control signal which controls the charging stage. In response to the charging control signal, the charging stage produces a window control signal for a predetermined period. The circuit includes a feedback network which injects the window control signal into the positive edge detector so that the positive edge detector is disabled while the window control signal is active.

摘要翻译： 一种适合制造为单片集成电路的自调整窗口电路。 自调整窗口电路包括输入端口，耦合到输入端口的上升沿检测器，耦合到边缘检测器的输出端的锁存器和耦合到锁存器的充电级。 输入信号包括具有以预定扫描速率出现的脉冲序列的信号，例如复合视频信号。 输入端口将输入信号馈送到边缘检测器，其响应于检测到输入信号中的脉冲而产生脉冲输出信号。 来自边缘检测器的脉冲输出被锁存并用于产生控制充电阶段的充电控制信号。 响应于充电控制信号，充电阶段产生预定时段的窗口控制信号。 电路包括反馈网络，其将窗口控制信号注入到上升沿检测器中，使得边沿检测器在窗口控制信号有效时被禁止。

公开(公告)号：US6154256A

公开(公告)日：2000-11-28

申请号：US712267

申请日：1996-09-11

申请人： Bryan Bruins

发明人： Bryan Bruins

IPC分类号： H04N5/08 ,  H04N5/16 ,  H04N9/44

CPC分类号： H04N5/08

摘要： A symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output. If the clamped video level drops suddenly, a delayed version of the fixed composite sync output clocks a flip flop, creating a fault signal which discharges a memory capacitor over a time period. When composite sync pulses are again sliced, the output from the first comparator resets the flip flop. The circuit also includes a video signal detector which enables its sync outputs only when it receives a predetermined number of valid lines of video with the frequency of the lines being in a predetermined range and with the last several lines being relatively free of noise. A timer prevents muting of the outputs if the input signal frequency is disturbed only momentarily.

摘要翻译： 在复合同步脉冲期间，对称钳位将输入视频信号钳位到参考电压，因此耦合电容放电电流在复合同步脉冲之间保持较小。 对于启动，非对称钳位采用运算放大器，二极管和可控电流源，以将耦合电容器充电至最小期望电平，并将电容器例如放电。 当直流电平发生变化时，输出电平过高。 还提供了一个使用两个比较器的同步切片检测器。 一个比较器将切片电平与钳位的视频进行比较，并产生适当切片的复合同步输出，而另一个比较钳位的视频与较小的参考电压，并产生固定的同步输出。 如果钳位的视频电平突然下降，固定复合同步输出的延迟版本会触发一个触发器，从而产生在一段时间内对存储电容器放电的故障信号。 当复合同步脉冲再次被分片时，来自第一比较器的输出复位触发器。 该电路还包括视频信号检测器，其仅当其接收到预定数量的有效线路的视频时，其线的频率在预定范围内，并且最后几行相对没有噪声才能使其同步输出。 如果输入信号频率仅被暂时干扰，则定时器防止输出的静音。

公开(公告)号：US5953069A

公开(公告)日：1999-09-14

申请号：US712279

申请日：1996-09-11

申请人： Bryan Bruins ,  Paul Moore

发明人： Bryan Bruins ,  Paul Moore

IPC分类号： H04N5/08 ,  H04N5/16 ,  H04N9/44

CPC分类号： H04N5/08

摘要： Sync separator and video detector circuits, including a sync tip clamp having symmetrical and non-symmetrical clamps. The symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output. If the clamped video level drops suddenly, a delayed version of the fixed composite sync output clocks a flip flop, creating a fault signal which discharges a memory capacitor over a time period. When composite sync pulses are again sliced, the output from the first comparator resets the flip flop. The circuit also includes a video signal detector which enables its sync outputs only when it receives a predetermined number of valid lines of video with the frequency of the lines being in a predetermined range and with the last several lines being relatively free of noise. This is performed by a counter which provides a full count on receipt of the predetermined number of lines, but which has its inputs cleared if the frequency is outside the desired range, and which has its most significant bit cleared if significant noise is present. A timer prevents muting of the outputs if the input signal frequency is disturbed only momentarily.

摘要翻译： 同步分离器和视频检测器电路，包括具有对称和非对称夹具的同步尖端夹具。 在复合同步脉冲期间，对称钳位将输入视频信号钳位到参考电压，因此耦合电容放电电流在复合同步脉冲之间保持较小。 对于启动，非对称钳位采用运算放大器，二极管和可控电流源，以将耦合电容器充电至最小期望电平，并将电容器例如放电。 当直流电平发生变化时，输出电平过高。 还提供了一个使用两个比较器的同步切片检测器。 一个比较器将切片电平与钳位的视频进行比较，并产生适当切片的复合同步输出，而另一个比较钳位的视频与较小的参考电压，并产生固定的同步输出。 如果钳位的视频电平突然下降，固定复合同步输出的延迟版本会触发一个触发器，从而产生在一段时间内对存储电容器放电的故障信号。 当复合同步脉冲再次被分片时，来自第一比较器的输出复位触发器。 该电路还包括视频信号检测器，其仅当其接收到预定数量的有效线路的视频时，其线的频率在预定范围内，并且最后几行相对没有噪声才能使其同步输出。 这由计数器执行，该计数器在接收到预定数量的线路时提供完全计数，但是如果频率在期望范围之外，其输入被清除，并且如果存在显着噪声，其最高有效位被清除。 如果输入信号频率仅被暂时干扰，则定时器防止输出的静音。