Anneal technique for reducing amount of electronic trap in gate oxide film of transistor

发明授权

US06187632B1 Anneal technique for reducing amount of electronic trap in gate oxide film of transistor 失效

标题翻译：减少晶体管栅极氧化膜中电子陷阱量的退火技术

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专利标题： Anneal technique for reducing amount of electronic trap in gate oxide film of transistor
专利标题（中）： 减少晶体管栅极氧化膜中电子陷阱量的退火技术
申请号： US08994134

申请日： 1997-12-19
公开(公告)号： US06187632B1

公开(公告)日： 2001-02-13
发明人: Susumu Shuto , Miwa Tanaka , Masahisa Sonoda , Toshiaki Idaka , Kenichi Sasaki , Seiichi Mori
申请人： Susumu Shuto , Miwa Tanaka , Masahisa Sonoda , Toshiaki Idaka , Kenichi Sasaki , Seiichi Mori
优先权： JP8-349753 19961227
主分类号： H01L2166
IPC分类号： H01L2166

Anneal technique for reducing amount of electronic trap in gate oxide film of transistor

摘要：

A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a bit line, an SiON film (passivation film), covering the silicon substrate and serving as an uppermost layer, is formed on an upper portion of the silicon substrate. Thereafter, annealing is performed to discharge water in the BPSG film to an outer portion of an LSI. The annealing is performed under a condition satisfying the following equation of t≧7.86×10−11×L2×exp (9115/T) where t is anneal time (minutes), L is a thickness (nm) of the passivation film, and T is anneal temperature (absolute temperature). Thereby, an amount of electronic trap in a gate oxide film of the transistor can be reduced.

摘要（中）：

在硅衬底上形成具有浮置栅极，控制栅极，漏极区域和源极区域的EEPROM的存储单元。此后，通过CVD形成覆盖存储单元的BPSG膜（层间绝缘膜）。在包括位线的线之后，在硅衬底的上部形成覆盖硅衬底并用作最上层的SiON膜（钝化膜）。此后，进行退火以将BPSG膜中的水排出到LSI的外部。退火在满足以下等式的条件下进行，其中t为退火时间（分钟），L为钝化膜的厚度（nm），T为退火温度（绝对温度）。由此，可以减少晶体管的栅极氧化膜中的电子阱的量。

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