公开(公告)号：US06187632B1

公开(公告)日：2001-02-13

申请号：US08994134

申请日：1997-12-19

申请人： Susumu Shuto ,  Miwa Tanaka ,  Masahisa Sonoda ,  Toshiaki Idaka ,  Kenichi Sasaki ,  Seiichi Mori

发明人： Susumu Shuto ,  Miwa Tanaka ,  Masahisa Sonoda ,  Toshiaki Idaka ,  Kenichi Sasaki ,  Seiichi Mori

IPC分类号： H01L2166

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/51 ,  Y10S438/902 ,  Y10S438/904

摘要： A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a bit line, an SiON film (passivation film), covering the silicon substrate and serving as an uppermost layer, is formed on an upper portion of the silicon substrate. Thereafter, annealing is performed to discharge water in the BPSG film to an outer portion of an LSI. The annealing is performed under a condition satisfying the following equation of t≧7.86×10−11×L2×exp (9115/T) where t is anneal time (minutes), L is a thickness (nm) of the passivation film, and T is anneal temperature (absolute temperature). Thereby, an amount of electronic trap in a gate oxide film of the transistor can be reduced.

摘要翻译： 在硅衬底上形成具有浮置栅极，控制栅极，漏极区域和源极区域的EEPROM的存储单元。 此后，通过CVD形成覆盖存储单元的BPSG膜（层间绝缘膜）。 在包括位线的线之后，在硅衬底的上部形成覆盖硅衬底并用作最上层的SiON膜（钝化膜）。 此后，进行退火以将BPSG膜中的水排出到LSI的外部。 退火在满足以下等式的条件下进行，其中t为退火时间（分钟），L为钝化膜的厚度（nm），T为退火温度（绝对温度）。 由此，可以减少晶体管的栅极氧化膜中的电子阱的量。

公开(公告)号：US20060234448A1

公开(公告)日：2006-10-19

申请号：US11405538

申请日：2006-04-18

申请人： Keisuke Yonehama ,  Seiichi Mori ,  Eiji Sakagami ,  Masahisa Sonoda

发明人： Keisuke Yonehama ,  Seiichi Mori ,  Eiji Sakagami ,  Masahisa Sonoda

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor device includes an element isolation insulating film, memory cell transistors formed in an element isolation region and having respective gate electrodes, and a stopper film for forming a contact, formed both on a sidewall of the gate electrode of each transistor and on the element isolation insulating film between the gate electrodes. A level difference is set between the upper surface of the element isolation insulating film and the upper surface of the semiconductor substrate in the element isolation region. The level difference is set so that a level difference between the gate electrodes is smaller than a level difference in the gate electrode. Furthermore, the surface of the semiconductor substrate in the drain contact formation region is located lower than the surface of the semiconductor substrate corresponding to the gate electrode.

摘要翻译： 半导体器件包括元件隔离绝缘膜，形成在元件隔离区中并具有各自的栅电极的存储单元晶体管，以及形成接触的阻挡膜，形成在每个晶体管的栅电极的侧壁和元件上 隔离绝缘膜之间的栅电极。 在元件隔离绝缘膜的上表面和元件隔离区域中的半导体衬底的上表面之间设置有电平差。 电平差被设定为使得栅电极之间的电平差小于栅电极中的电平差。 此外，漏极接触形成区域中的半导体衬底的表面位于比对应于栅电极的半导体衬底的表面更低的位置。

公开(公告)号：US07026683B2

公开(公告)日：2006-04-11

申请号：US10642666

申请日：2003-08-19

申请人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Seiichi Mori

发明人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Seiichi Mori

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating electrodes formed along a first direction on the gate insulating film, a plurality of grooves formed among the plurality of floating electrodes, groove insulating films filled in the plurality of the grooves, a second conductive type impurity diffusion region formed along a second direction so as to sandwich the floating electrodes, interelectrode insulating films formed along the first direction on the plurality of floating electrodes and the groove insulating films, and control electrodes formed on the interelectrode insulating films.

摘要翻译： 多个非易失性存储元件，形成在由第一导电型半导体衬底的主表面上的元件隔离区分隔开的元件区域上，所述非易失性半导体存储元件包括形成在半导体衬底的主表面上的栅极绝缘膜，多个 在所述栅极绝缘膜上沿着第一方向形成的浮置电极，在所述多个浮置电极之间形成的多个沟槽，填充在所述多个沟槽中的沟槽绝缘膜，沿着第二方向形成的第二导电型杂质扩散区域， 夹着浮动电极，在多个浮置电极和沟槽绝缘膜上沿着第一方向形成的电极间绝缘膜，以及形成在电极间绝缘膜上的控制电极。

公开(公告)号：US07557401B2

公开(公告)日：2009-07-07

申请号：US11405538

申请日：2006-04-18

申请人： Keisuke Yonehama ,  Seiichi Mori ,  Eiji Sakagami ,  Masahisa Sonoda

发明人： Keisuke Yonehama ,  Seiichi Mori ,  Eiji Sakagami ,  Masahisa Sonoda

IPC分类号： H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor device includes an element isolation insulating film adjacent to an active area, a gate insulating film formed on a semiconductor substrate in the active area, paired gate electrodes located on the gate insulating film, a contact plug located on the active area between the gate electrodes, a pair of first upper lines located on the gate electrodes, a second upper line located on the gate electrodes, and a stopper film above upper surfaces of the gate electrodes and side surfaces of the gate electrodes. The element isolation insulating film has a first height of an upper surface thereof with reference to an upper surface of the semiconductor substrate and a second height of another upper surface thereof with reference to another upper surface of the semiconductor substrate. The first height is smaller than the second height.

摘要翻译： 半导体器件包括与有源区相邻的元件隔离绝缘膜，形成在有源区中的半导体衬底上的栅极绝缘膜，位于栅极绝缘膜上的成对栅电极，位于栅极之间的有源区上的接触插塞 电极，位于栅极电极上的一对第一上部线，位于栅电极上的第二上部线，以及栅电极的上表面和栅电极的侧表面之上的阻挡膜。 元件隔离绝缘膜相对于半导体衬底的上表面具有上表面的第一高度，并且相对于半导体衬底的另一上表面具有另一上表面的第二高度。 第一个高度小于第二个高度。

公开(公告)号：US20060081907A1

公开(公告)日：2006-04-20

申请号：US11290461

申请日：2005-12-01

申请人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Seiichi Mori

发明人： Masahisa Sonoda ,  Hiroaki Tsunoda ,  Seiichi Mori

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating electrodes formed along a first direction on the gate insulating film, a plurality of grooves formed among the plurality of floating electrodes, groove insulating films filled in the plurality of the grooves, a second conductive type impurity diffusion region formed along a second direction so as to sandwich the floating electrodes, interelectrode insulating films formed along the first direction on the plurality of floating electrodes and the groove insulating films, and control electrodes formed on the interelectrode insulating films.

公开(公告)号：US20110186921A1

公开(公告)日：2011-08-04

申请号：US13085884

申请日：2011-04-13

申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

摘要翻译： 公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜 所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上， 元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子 经由开口部与第一电极层连接。

公开(公告)号：US07258096B2

公开(公告)日：2007-08-21

申请号：US11359454

申请日：2006-02-23

申请人： Seiichi Mori ,  Manabu Enari

发明人： Seiichi Mori ,  Manabu Enari

IPC分类号： F01M11/03 ,  F02B75/22

CPC分类号： F01M11/03 ,  F01M2001/1064

摘要： The number of constituent parts for an oil filter fixing system such as a bracket, are reduced, and the oil leaks during filter element exchange are avoided. The oil filter fixing system comprises a V bank of a V type engine, a crankcase fixed with the V bank and an oil filter fixed with the crankcase. A horizontal fixing plane is formed at a part of an outer surface of the crankcase and the oil filter is directly fixed with and hung down from the horizontal plane. Further, the horizontal fixing plane is provided at an outer surface of the crankcase and moreover under a cam fixing portion provided in the crankcase. The oil filter is disposed in a space which is formed by the horizontal fixing plane and a lower vertical side surface of the crankcase.

摘要翻译： 用于诸如支架的油过滤器固定系统的组成部件的数量减少，并且避免在过滤元件更换期间的油泄漏。 油过滤器固定系统包括V型发动机的V组，与V组固定的曲轴箱和固定有曲轴箱的油过滤器。 在曲轴箱的外表面的一部分处形成水平固定平面，并且油滤器直接与水平面固定并悬挂在水平面上。 此外，水平固定平面设置在曲轴箱的外表面处，并且还设置在设置在曲轴箱中的凸轮固定部分下方。 油过滤器设置在由水平固定平面和曲轴箱的下垂直侧面形成的空间中。

公开(公告)号：US20070190727A1

公开(公告)日：2007-08-16

申请号：US11783368

申请日：2007-04-09

申请人： Hiroaki Hazama ,  Seiichi Mori ,  Hirohisa Iizuka ,  Norio Ootani ,  Kazuhito Narita

发明人： Hiroaki Hazama ,  Seiichi Mori ,  Hirohisa Iizuka ,  Norio Ootani ,  Kazuhito Narita

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7881

摘要： A method of manufacturing a nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit and also including forming a first well for a memory cell and a second well for the MOS transistor in a semiconductor substrate.

摘要翻译： 一种制造在外围电路中包括至少一个MOS晶体管的非易失性半导体存储器件的方法，还包括在半导体衬底中形成用于存储单元的第一阱和用于MOS晶体管的第二阱。

公开(公告)号：US20070057315A1

公开(公告)日：2007-03-15

申请号：US11556299

申请日：2006-11-03

申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

公开(公告)号：US07141474B2

公开(公告)日：2006-11-28

申请号：US11008531

申请日：2004-12-10

申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an opening in a part of the inter-gate insulating layer; depositing a control gate electrode on the inter-gate insulating layer and an exposed portion of the first conductive layer by the opening; and forming the gate electrodes of the memory cell transistors and the gate electrodes of the select transistors by utilizing the etching processes of the control gate electrode, the inter-gate insulating layer and the first conductive layer, wherein the select transistors include at least a part of the exposed portion of the first conductive layer.

摘要翻译： 一种制造非易失性半导体存储器的方法，包括以下步骤：在半导体衬底上依次形成栅极绝缘层和浮置栅极的第一导电层; 沉积栅极间绝缘层; 在所述栅极绝缘层的一部分中形成开口; 通过所述开口在所述栅极间绝缘层上沉积控制栅极电极和所述第一导电层的暴露部分; 以及通过利用所述控制栅电极，所述栅极间绝缘层和所述第一导电层的蚀刻工艺，形成所述存储单元晶体管的栅电极和所述选择晶体管的栅电极，其中所述选择晶体管至少包括一部分 的第一导电层的暴露部分。