A data output circuit for a semiconductor memory device, such as a synchronous DRAM (SDRAM) includes an output control circuit that acquires a command in sync with an input internal clock signal and generates an output control signal used to determine the output timing of a data signal. An output buffer receives the output control signal and then outputs the data signal in accordance with an output internal clock signal. The phase of the output internal clock signal is advanced from that of the input internal clock signal. The output control circuit also includes a latency counter that generates the output control signal by counting the cycles of a second output internal clock signal, which is delayed from the first output internal clock signal.