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    Data output circuits for semiconductor memory devices
    1.
    发明授权
    Data output circuits for semiconductor memory devices 有权
    半导体存储器件的数据输出电路

    公开(公告)号：US06188640B1

    公开(公告)日：2001-02-13

    申请号：US09398828

    申请日：1999-09-17

    申请人： Tadao Aikawa ,  Yasuharu Sato ,  Hiroyuki Kobayashi ,  Waichirou Fujieda

    发明人： Tadao Aikawa ,  Yasuharu Sato ,  Hiroyuki Kobayashi ,  Waichirou Fujieda

    IPC分类号： G11C800

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4093

    摘要： A data output circuit for a semiconductor memory device, such as a synchronous DRAM (SDRAM) includes an output control circuit that acquires a command in sync with an input internal clock signal and generates an output control signal used to determine the output timing of a data signal. An output buffer receives the output control signal and then outputs the data signal in accordance with an output internal clock signal. The phase of the output internal clock signal is advanced from that of the input internal clock signal. The output control circuit also includes a latency counter that generates the output control signal by counting the cycles of a second output internal clock signal, which is delayed from the first output internal clock signal.

    摘要翻译： 用于诸如同步DRAM（SDRAM）的半导体存储器件的数据输出电路包括输出控制电路，其获取与输入的内部时钟信号同步的命令，并且生成用于确定数据的输出定时的输出控制信号 信号。 输出缓冲器接收输出控制信号，然后根据输出内部时钟信号输出数据信号。 输出内部时钟信号的相位从输入内部时钟信号的相位提前。 输出控制电路还包括延迟计数器，其通过对从第一输出内部时钟信号延迟的第二输出内部时钟信号的周期进行计数来产生输出控制信号。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06459641B2

    公开(公告)日：2002-10-01

    申请号：US09834945

    申请日：2001-04-16

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    IPC分类号： G11C700

    CPC分类号： G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

    摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

    摘要翻译： 本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US6088291A

    公开(公告)日：2000-07-11

    申请号：US147600

    申请日：1999-01-29

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C7/06 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C2207/005 ,  G11C2207/065

    摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

    摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。 第WO98 / 56004号公报 日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

    Semiconductor memory circuit having selective redundant memory cells
    5.
    发明授权
    Semiconductor memory circuit having selective redundant memory cells 有权
    具有选择性冗余存储单元的半导体存储器电路

    公开(公告)号：US06496430B2

    公开(公告)日：2002-12-17

    申请号：US10131221

    申请日：2002-04-25

    申请人： Tadao Aikawa ,  Takaaki Suzuki ,  Yasuharu Sato ,  Hiroyuki Kobayashi

    发明人： Tadao Aikawa ,  Takaaki Suzuki ,  Yasuharu Sato ,  Hiroyuki Kobayashi

    IPC分类号： G11C2900

    CPC分类号： G11C29/808

    摘要： A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.

    摘要翻译： 半导体存储器电路包括以行和列排列的多个存储单元阵列。 解码器电路从多个存储单元阵列中选择预定数量的存储单元阵列。 感测放大器感测从选定的存储单元阵列读取的数据。 多个存储单元阵列被分组成第一类型的存储单元阵列，每个存储单元阵列具有冗余存储单元和每个不具有冗余存储单元的第二类型存储单元阵列。

    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations
    9.
    发明授权
    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
    半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作

    公开(公告)号：US06427197B1

    公开(公告)日：2002-07-30

    申请号：US09394891

    申请日：1999-09-13

    申请人： Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    发明人： Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C7/1039

    摘要： The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.

    摘要翻译： 本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址 写命令 第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。 根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。 此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

    Semiconductor memory device with reduced power consumption
    10.
    发明授权
    Semiconductor memory device with reduced power consumption 失效
    具有降低功耗的半导体存储器件

    公开(公告)号：US06191999B1

    公开(公告)日：2001-02-20

    申请号：US08993139

    申请日：1997-12-18

    申请人： Waichirou Fujieda ,  Shinya Fujioka ,  Tadao Aikawa

    发明人： Waichirou Fujieda ,  Shinya Fujioka ,  Tadao Aikawa

    IPC分类号： G11C800

    CPC分类号： G11C8/14 ,  G11C8/10

    摘要： A semiconductor memory device using hierarchical word decoding for word selection includes memory-cell areas, each of which is provided for a corresponding one of column blocks. The semiconductor memory device further includes sub-word lines provided for each one of the column blocks and extending over a corresponding one of the memory-cell areas, and sub-word decoders provided on either side of a given one of the memory-cell areas to select one of the sub-word lines only with respect to the given one of the memory-cell areas.

    摘要翻译： 使用用于字选择的分层字解码的半导体存储器件包括存储单元区域，每个区域被提供给相应的列块。 半导体存储器件还包括为每个列块提供的子字线，并且在相应的一个存储单元区域上延伸，并且在给定的一个存储单元区域的两侧提供的子字解码器 仅相对于给定的一个存储单元区域来选择一个子字线。