发明授权
US06230293B1 Method for quality and reliability assurance testing of integrated circuits using differential Iddq screening in lieu of burn-in
失效
使用差分Iddq筛选代替老化的集成电路的质量和可靠性保证测试方法
- 专利标题： Method for quality and reliability assurance testing of integrated circuits using differential Iddq screening in lieu of burn-in
- 专利标题（中）： 使用差分Iddq筛选代替老化的集成电路的质量和可靠性保证测试方法
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申请号： US09121991申请日： 1998-07-24
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公开(公告)号： US06230293B1公开(公告)日： 2001-05-08
- 发明人: Sailesh Chittipeddi , Daryl E. Diehl , Thomas N. Hofacker , Richard J. Jenkins , Mamata Patnaik , Robert T. Smith , Michael J. Toth , Keelathur N. Vasudevan , Michael Washko
- 申请人： Sailesh Chittipeddi , Daryl E. Diehl , Thomas N. Hofacker , Richard J. Jenkins , Mamata Patnaik , Robert T. Smith , Michael J. Toth , Keelathur N. Vasudevan , Michael Washko
- 主分类号： G01R3128
- IPC分类号： G01R3128
摘要：
A method for quality and reliability assurance testing a lot of fabricated ICs comprising the steps of testing the differential Iddq of a sample of ICs at a plurality of different voltages, burning-in a sample of ICs, and then testing the functionality of the sample of ICs. The method of the present invention enables the reliability of an entire lot of ICs to be tested by determining an effective screening voltage for differential Iddq testing of the ICs, thereby eliminating the need both to burn-in and conduct post burn-in testing of all future lots of the ICs. The method of the present invention also enables fabrication facilities and workers to be engaged in other tasks rather than testing of ICs.
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