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    Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer
    3.
    发明授权
    Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer 有权
    绝缘体上硅（SOI）半导体结构，具有包括导电层的附加沟槽

    公开(公告)号：US06538283B1

    公开(公告)日：2003-03-25

    申请号：US09611907

    申请日：2000-07-07

    申请人： Sailesh Chittipeddi ,  Michael J. Kelly

    发明人： Sailesh Chittipeddi ,  Michael J. Kelly

    IPC分类号： H01L2701

    CPC分类号： H01L29/66181 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/0805 ,  H01L27/1203

    摘要： A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, and a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the base substrate, the insulator layer and the silicon layer, wherein the at least one trench includes at least one layer of silicon dioxide formed therein. In a preferred embodiment, semiconductor material disposed in the at least one trench forms a first electrode of a semiconductor capacitor, and semiconductor material of the SOI substrate which lies adjacent to the at least one trench forms a second electrode of the capacitor.

    摘要翻译： 一种包括绝缘体上硅（SOI）衬底的半导体器件，包括基底衬底，绝缘体层和硅层，以及沟槽电容器，其包括形成在绝缘体上硅衬底中的至少一个沟槽， 基底衬底，绝缘体层和硅层，其中至少一个沟槽包括在其中形成的至少一层二氧化硅。 在优选实施例中，设置在至少一个沟槽中的半导体材料形成半导体电容器的第一电极，并且位于与至少一个沟槽相邻的SOI衬底的半导体材料形成电容器的第二电极。

    Transistor fabrication method
    4.
    发明授权
    Transistor fabrication method 失效
    晶体管制造方法

    公开(公告)号：US06498080B1

    公开(公告)日：2002-12-24

    申请号：US08587061

    申请日：1996-01-16

    申请人： Sailesh Chittipeddi ,  Taeho Kook ,  Avinoam Kornblit

    发明人： Sailesh Chittipeddi ,  Taeho Kook ,  Avinoam Kornblit

    IPC分类号： H01L213205

    CPC分类号： H01L29/66575 ,  H01L21/0276 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

    摘要翻译： 公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。 使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。 可以形成各种硅化和非硅化的结构。

    Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers
    5.
    发明授权
    Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
    包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构

    公开(公告)号：US06482694B2

    公开(公告)日：2002-11-19

    申请号：US09878657

    申请日：2001-06-11

    申请人： Sailesh Chittipeddi ,  Charles Walter Pearce

    发明人： Sailesh Chittipeddi ,  Charles Walter Pearce

    IPC分类号： H01L218242

    CPC分类号： H01L28/40 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/3185 ,  H01L27/0805 ,  H01L27/1085

    摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.

    摘要翻译： 绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止钽的扩散。 提供高介电常数。 绝缘结构的热稳定性提高。 绝缘结构可以包括在电容器或浅沟槽隔离结构中。 示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。 下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。 上电极可以是TiN层或多晶硅层。 示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。 浅沟槽中填充有氧化物，如TEOS。 可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。

    Process for forming gate oxides possessing different thicknesses on a semiconductor substrate
    8.
    发明授权
    Process for forming gate oxides possessing different thicknesses on a semiconductor substrate 失效
    在半导体衬底上形成具有不同厚度的栅极氧化物的工艺

    公开(公告)号：US5918116A

    公开(公告)日：1999-06-29

    申请号：US853210

    申请日：1997-05-09

    申请人： Sailesh Chittipeddi

    发明人： Sailesh Chittipeddi

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/28185 ,  H01L21/28211 ,  H01L21/823462 ,  Y10S438/981

    摘要： Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises forming a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions.The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

    摘要翻译： 具有不同厚度的栅极氧化物通过包括在衬底上形成半导体层的方法在半导体层上生长，在半导体层上生长氧化物层，暴露氧化物层的选定区域，将暴露的氧化物下面的半导体层非晶化 去除氧化物层以暴露具有非晶化区域和非非晶化区域的半导体层，并且在半导体层的非晶化和非非晶化区域上生长栅极氧化物。 在非晶化区域上生长的栅极氧化物将比在非非晶化区域上生长的栅极氧化物厚。 本发明的方法避免了对专用集成电路制造设计修改的需要，并且可以用于制造各种各样的器件，特别是MOS型器件。

    Process for forming integrated capacitors
    10.
    发明授权
    Process for forming integrated capacitors 失效
    形成集成电容器的工艺

    公开(公告)号：US5589416A

    公开(公告)日：1996-12-31

    申请号：US568040

    申请日：1995-12-06

    申请人： Sailesh Chittipeddi

    发明人： Sailesh Chittipeddi

    IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70

    CPC分类号： H01L28/55 ,  H01L28/60 ,  Y10S148/014

    摘要： Disclosed is a technique for forming integrated capacitors using a sequence of process steps that is fully compatible with standard silicon gate MOS integrated circuit processing. The capacitor comprises a polysilicon-oxide-TiN/metal combination. The lower plate, i.e. polysilicon plate, is interconnected at the gate level and the upper plate is interconnected typically at metal one.

    摘要翻译： 公开了一种使用与标准硅栅极MOS集成电路处理完全兼容的一系列工艺步骤形成集成电容器的技术。 电容器包括多晶硅氧化物TiN /金属组合。 下板，即多晶硅板，在栅极级互连，上板通常以金属互连。