A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.