公开(公告)号：US06240043B1

公开(公告)日：2001-05-29

申请号：US09456588

申请日：1999-12-08

申请人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

发明人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

IPC分类号： G11C800

CPC分类号： G11C7/1006 ,  G11C7/1021

摘要： A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.

摘要翻译： 包括在集成电路中的随机存取存储器（RAM），特别是具有可屏蔽数据输入的同步动态RAM（SDRAM）。 SDRAM包括一个xy数据输入寄存器，它接收与数据线（DQ）数量相对应的突发x位长和y位宽。 xy屏蔽寄存器接收每个接收数据位的相应掩码位，每个掩码位指示对应的数据位是否存储在SDRAM阵列中。 使能缓冲器从xy数据输入寄存器接收数据输出，并根据存储在xy掩码寄存器中的相应屏蔽状态将各个数据输出传递给阵列。 掩模寄存器优选设置为掩蔽状态。 当使能信号被逐位置信时，会发生解掩码。 当允许写突发中断命令被断言时，允许脉冲串长度内的其余位处于屏蔽状态。 在输入预取期间，可能会发生中断，导致突发或预取的任何接收的部分被存储在阵列中，而不会干扰对应于预取的余额或剩余比特的存储器位置。

公开(公告)号：US6140855A

公开(公告)日：2000-10-31

申请号：US281461

申请日：1999-03-30

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  David R. Hanson

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  David R. Hanson

IPC分类号： H03K19/0175 ,  G06F13/28 ,  G11C7/10 ,  G11C11/407 ,  H04L25/02 ,  H04L25/03 ,  H03K3/356

CPC分类号： G11C7/1087 ,  G11C7/1078

摘要： A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device and overlapping in time with a prior generated first pointer signal of the sequence; and, a pulse converter device associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.

摘要翻译： 动态锁存接收器装置包括并行排列的一系列数据锁存装置，用于使能顺序锁存在单个数据线上串行通信的数据信号。 该装置包括用于产生一个或多个第一指针信号的序列的第一指针信号发生器，每个产生与特定锁存装置相对应的序列的第一指针信号，并且与该序列的先前生成的第一指针信号在时间上重叠; 以及与锁存装置相关联的脉冲转换器装置，用于接收对应的第一指针信号并产生相应的第二指针信号以输入到相应的锁存装置，每个第二指针信号以不重叠的顺序产生，用于触发相应的锁存 每个数据信号与串行数据信号同步。

公开(公告)号：US06522171B2

公开(公告)日：2003-02-18

申请号：US09759011

申请日：2001-01-11

申请人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

发明人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

IPC分类号： H03K19096

CPC分类号： H03K19/0016 ,  H03K19/0963

摘要： A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

公开(公告)号：US06292402B1

公开(公告)日：2001-09-18

申请号：US09456589

申请日：1999-12-08

申请人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

发明人： David R. Hanson ,  Toshiaki Kirihata ,  Gerhard Mueller

IPC分类号： G11C1604

CPC分类号： G11C7/1072 ,  G11C7/1078

摘要： A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

摘要翻译： 用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。 预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。 预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。 数据级和使能级可以各自包括两个或多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。 当数据通过数据阶段时，相应的使能状态通过使能阶段。 如果使能状态指示要将数据级中的数据写入阵列，则将数据传送到RAM阵列。

公开(公告)号：US06954387B2

公开(公告)日：2005-10-11

申请号：US10604375

申请日：2003-07-15

申请人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

发明人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

IPC分类号： G11C11/406 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

公开(公告)号：US6115308A

公开(公告)日：2000-09-05

申请号：US335092

申请日：1999-06-17

申请人： David R. Hanson ,  Toshiaki Kirihata

发明人： David R. Hanson ,  Toshiaki Kirihata

IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/419 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C7/1039 ,  G11C7/06

摘要： A method of performing overlapping operations with a memory device may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. The method may include applying a first equalize signal and second equalize signal to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines, applying a switch signal to the sense amplifier circuit to connect the data bus lines to a read data bus, and changing a state of the first equalize signal such that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.

摘要翻译： 与存储器件执行重叠操作的方法可以具有读出放大器电路和连接到读出放大器电路的两个驱动器。 两条数据总线可以连接到读出放大器电路以接收数据信号。 该方法可以包括将第一均衡信号和第二均衡信号施加到读出放大器电路，以允许读出放大器电路跨数据总线接收数据信号，将开关信号施加到读出放大器电路以连接数据总线 读取数据总线，并且改变第一均衡信号的状态，使得数据总线线路接收新数据或数据总线线路均等于预定电压，同时数据位于读数据总线上并且能够被 读。

公开(公告)号：US06690198B2

公开(公告)日：2004-02-10

申请号：US10114195

申请日：2002-04-02

申请人： Gerhard Mueller ,  Toshiaki Kirihata

发明人： Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： H03K190175

CPC分类号： H03K19/01721 ,  G11C7/1048 ,  G11C7/1069 ,  G11C11/4096 ,  H03K19/0013

摘要： A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

摘要翻译： 描述了具有改进的开关速度和降低的功耗的中继器电路。 中继器电路被配置为从信号线的第一段接收输入信号，并且响应于主动控制信号将信号传递到信号线的第二段。

公开(公告)号：US5831912A

公开(公告)日：1998-11-03

申请号：US938074

申请日：1997-09-26

申请人： Gerhard Mueller ,  Toshiaki Kirihata

发明人： Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C5/025 ,  G11C11/4097 ,  G11C7/18

摘要： The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

摘要翻译： 本公开包括具有空间有效布局的半导体存储器。 动态随机存取存储器（DRAM）芯片具有以行和列排列的多个存储单元（18）。 半导体存储器包括设置在具有与所述行平行的长度的第一大致矩形区域中的读出放大器组，其中每个读出放大器（14）设置在相关联的列（16）的读出放大器区域中， 。 多个放大器（124或126）由至少一个驱动器（140或142）驱动，多个放大器中的每个放大器设置在一对互补位线（120）之间并位于读出放大器区域内。 至少一个驱动器至少与至少一个驱动器共享至少一个横向于列方向延伸的扩散区域，使得读出放大器组的触点数量减少。

公开(公告)号：US07146471B2

公开(公告)日：2006-12-05

申请号：US10748333

申请日：2003-12-31

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

IPC分类号： G06F12/02

CPC分类号： G06F13/1694 ,  Y02D10/14

摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

摘要翻译： 公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。 示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。 当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。 通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

公开(公告)号：US6081479A

公开(公告)日：2000-06-27

申请号：US333539

申请日：1999-06-15

申请人： Brian Ji ,  Toshiaki Kirihata ,  Gerhard Mueller ,  David Hanson

发明人： Brian Ji ,  Toshiaki Kirihata ,  Gerhard Mueller ,  David Hanson

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1039

摘要： A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

摘要翻译： 根据本发明的半导体存储器包括包括多个分层级的数据路径，每个级包括与其他级不同的位数据速率。 至少两个预取电路设置在各级之间。 至少两个预取电路包括用于接收数据位并存储数据位的至少两个锁存器，直到层级中的下一级能够接收数据位。 所述至少两个预取电路耦合在级之间，使得级之间每级的总体数据速率基本相等。 控制信号控制至少两个锁存器，使得预取电路保持级之间的总体数据速率。