A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: a) growing a sacrificial oxide layer on a substrate; b) implanting a dopant through the sacrificial oxide layer; c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; f) implanting a second dosage of nitrogen ions through the photoresist; g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.