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208 条记录 (耗时 0.026 秒)

    Dual gate oxide process for uniform oxide thickness
    1.
    发明授权
    Dual gate oxide process for uniform oxide thickness 有权
    双栅氧化法，均匀氧化物厚度

    公开(公告)号：US06261972B1

    公开(公告)日：2001-07-17

    申请号：US09706641

    申请日：2000-11-06

    申请人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

    发明人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

    IPC分类号： H01L2100

    CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

    摘要： A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: a) growing a sacrificial oxide layer on a substrate; b) implanting a dopant through the sacrificial oxide layer; c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; f) implanting a second dosage of nitrogen ions through the photoresist; g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

    摘要翻译： 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以允许氮扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双栅氧化物的薄氧化物的位置; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

    Vertical hard mask
    3.
    发明授权
    Vertical hard mask 失效
    垂直硬面罩

    公开(公告)号：US06723611B2

    公开(公告)日：2004-04-20

    申请号：US10241225

    申请日：2002-09-10

    申请人： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

    发明人： Hiroyuki Akatsu ,  Oleg Gluschenkov ,  Porshia S. Parkinson ,  Ravikumar Ramachandran ,  Helmut Horst Tews ,  Kenneth T. Settlemyer, Jr.

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087

    摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

    摘要翻译： 在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在 下部。

    Gate processing method with reduced gate oxide corner and edge thinning
    4.
    发明授权
    Gate processing method with reduced gate oxide corner and edge thinning 有权
    栅极处理方法具有减少的栅氧化物角和边缘变薄

    公开(公告)号：US06656798B2

    公开(公告)日：2003-12-02

    申请号：US09965919

    申请日：2001-09-28

    申请人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

    发明人： Helmut Tews ,  Oleg Gluschenkov ,  Mary Weybright

    IPC分类号： H01L21336

    CPC分类号： H01L29/517 ,  H01L21/28238 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/42368

    摘要： Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

    摘要翻译： 公开了一种在半导体晶片上处理半导体栅极结构的方法，该方法包括提供半导体结构，该半导体结构具有覆盖有由一个或多个隔离沟槽限定的焊盘氧化物层的有源器件区域，通过增厚所述焊盘来提供牺牲氧化物层 使用所述增厚衬垫氧化物层作为用于器件注入的牺牲氧化物层，在使用之后剥离所述牺牲衬垫氧化物层，并用最终栅极氧化物层封装所述半导体栅极。

    Alignment data based process control system
    5.
    发明授权
    Alignment data based process control system 有权
    基于对齐数据的过程控制系统

    公开(公告)号：US09360858B2

    公开(公告)日：2016-06-07

    申请号：US13204955

    申请日：2011-08-08

    申请人： Christopher P. Ausschnitt ,  Timothy A. Brunner ,  Allen H. Gabor ,  Oleg Gluschenkov ,  Vinayan C. Menon

    发明人： Christopher P. Ausschnitt ,  Timothy A. Brunner ,  Allen H. Gabor ,  Oleg Gluschenkov ,  Vinayan C. Menon

    IPC分类号： G06F19/00 ,  G05B19/401

    CPC分类号： G05B19/401 ,  G05B2219/2602 ,  G05B2219/45031

    摘要： Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.

    摘要翻译： 通过在一个或多个处理步骤之前和之后的光刻处理步骤中测量衬底对准数据来确定由于一个或多个处理步骤导致的衬底的变形。 通过将计算的对准数据差异与在数据库中累积的先前数据进行比较来识别对准数据差异中的任何异常模式。 通过将异常模式与先前识别的针对对准数据差异的工具特定模式进行比较，可以识别引入异常模式和/或异常处理性质的处理步骤，并且可以采取适当的过程控制措施来纠正任何异常 在所识别的处理步骤中。

    Structure and method for mobility enhanced MOSFETs with unalloyed silicide
    7.
    发明授权
    Structure and method for mobility enhanced MOSFETs with unalloyed silicide 有权
    具有非合金化硅化物的迁移率增强型MOSFET的结构和方法

    公开(公告)号：US08217423B2

    公开(公告)日：2012-07-10

    申请号：US11619809

    申请日：2007-01-04

    申请人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R Holt ,  Renee T Mo ,  Kern Rim

    发明人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R Holt ,  Renee T Mo ,  Kern Rim

    IPC分类号： H01L27/082

    CPC分类号： H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

    摘要翻译： 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

    Inline low-damage automated failure analysis
    9.
    发明授权
    Inline low-damage automated failure analysis 有权
    内联低损伤自动化故障分析

    公开(公告)号：US08111903B2

    公开(公告)日：2012-02-07

    申请号：US12238602

    申请日：2008-09-26

    申请人： Steven B. Herschbein ,  Ronald C. Geiger, Jr. ,  George Y. Gu ,  Oleg Gluschenkov ,  Xu Ouyang

    发明人： Steven B. Herschbein ,  Ronald C. Geiger, Jr. ,  George Y. Gu ,  Oleg Gluschenkov ,  Xu Ouyang

    IPC分类号： G06K9/00

    CPC分类号： G06T7/0004 ,  G06T2207/10061 ,  G06T2207/30148

    摘要： A system and method for failure analysis of devices on a semiconductor wafer is disclosed. The present invention comprises the use of an inline focused ion beam milling tool to perform milling and image capturing of cross sections of a desired inspection point. The inspection points are located by identifying at least one fiducial that corresponds to an X-Y offset from the desired inspection point. The fiducials are recognized by a computer vision system. By automating the inspection process, the time required to perform the inspections is greatly reduced.

    摘要翻译： 公开了一种用于半导体晶片上的器件的故障分析的系统和方法。 本发明包括使用在线聚焦离子束铣削工具来执行所需检查点的横截面的铣削和图像捕获。 通过识别与期望的检查点的X-Y偏移对应的至少一个基准来定位检查点。 基准由计算机视觉系统认可。 通过自动化检查过程，进行检查所需的时间大大减少。

    Source/drain junction for high performance MOSFET formed by selective EPI process
    10.
    发明授权
    Source/drain junction for high performance MOSFET formed by selective EPI process 有权
    通过选择性EPI工艺形成的高性能MOSFET的源极/漏极结

    公开(公告)号：US07932136B2

    公开(公告)日：2011-04-26

    申请号：US12109025

    申请日：2008-04-24

    申请人： Xuefeng Hua ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Oleg Gluschenkov

    发明人： Xuefeng Hua ,  Johnathan E. Faltermeier ,  Toshiharu Furukawa ,  Oleg Gluschenkov

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66636 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78609 ,  H01L29/78621 ,  H01L29/78696

    摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.

    摘要翻译： 在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。 源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。 通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。 这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。