发明授权
US06265291B1 Circuit fabrication method which optimizes source/drain contact resistance 有权
优化源极/漏极接触电阻的电路制造方法

  • 专利标题: Circuit fabrication method which optimizes source/drain contact resistance
  • 专利标题(中): 优化源极/漏极接触电阻的电路制造方法
  • 申请号: US09224754
    申请日: 1999-01-04
  • 公开(公告)号: US06265291B1
    公开(公告)日: 2001-07-24
  • 发明人: Bin YuEmi Ishida
  • 申请人: Bin YuEmi Ishida
  • 主分类号: H01L2104
  • IPC分类号: H01L2104
Circuit fabrication method which optimizes source/drain contact resistance
摘要:
A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.
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