公开(公告)号：US06472283B1

公开(公告)日：2002-10-29

申请号：US09667787

申请日：2000-09-22

申请人： Emi Ishida ,  Srinath Krishman ,  Ming Yin Hao ,  Effiong Ibok

发明人： Emi Ishida ,  Srinath Krishman ,  Ming Yin Hao ,  Effiong Ibok

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

摘要翻译： 亚微米尺寸的MOS和/或CMOS晶体管通过采用由诸如UV氮化物的材料制成的可移除的侧壁间隔的工艺制造，其易于以其沉积的未增稠的状态蚀刻，但在其热 退火，致密化状态。 通过在植入中等或重掺杂的源极/漏极区域之后但在用于掺杂剂扩散/激活和晶格损伤弛豫的植入物退火之前用稀释的HF水溶液去除沉积的未增塑的间隔物。 轻微或中度掺杂的浅深度源极/漏极延伸部分在去除间隔物之后被植入和退火。

公开(公告)号：US06444550B1

公开(公告)日：2002-09-03

申请号：US09640177

申请日：2000-08-17

申请人： Ming-Yin Hao ,  Emi Ishida

发明人： Ming-Yin Hao ,  Emi Ishida

IPC分类号： H01L21425

CPC分类号： H01L29/105 ,  H01L21/268 ,  Y10S438/914

摘要： A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to “reverse short channel effects.”

摘要翻译： 具有逆行通道轮廓的半导体器件通过在半导体衬底的表面部分中形成逆向杂质区域，随后在逆向杂质区域上以预定厚度形成半导体层来实现。 控制半导体层的厚度以将逆向杂质区域和其杂质浓度峰值定位在预定深度，从而减少器件对“反向短沟道效应”的敏感性。

公开(公告)号：US06426279B1

公开(公告)日：2002-07-30

申请号：US09598911

申请日：2000-06-22

申请人： Carl Huster ,  Emi Ishida

发明人： Carl Huster ,  Emi Ishida

IPC分类号： H01L21425

CPC分类号： H01L29/105 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26506 ,  H01L29/6659

摘要： A semiconductor device exhibiting a super-steep retrograde channel profile to reduce susceptibility to “latch up” is achieved by forming a high impurity concentration layer on a semiconductor substrate and forming a diffusion cap layer near the surface of the high impurity concentration layer. Subsequently, a low impurity concentration layer is formed on the diffusion cap layer of the high impurity concentration layer. The diffusion cap layer formed between the high and low impurity concentration layers substantially prevents the impurities contained in the high impurity concentration layer from diffusing into the overlying low impurity concentration layer, thereby achieving a super-steep retrograde channel profile.

摘要翻译： 通过在半导体衬底上形成高杂质浓度层并在高杂质浓度层的表面附近形成扩散覆盖层，实现了表现出陡峭逆向沟道轮廓以减小“闩锁”敏感性的半导体器件。 接着，在高杂质浓度层的扩散覆盖层上形成低杂质浓度层。 形成在高杂质浓度层和低杂质浓度层之间的扩散帽层基本上防止了高杂质浓度层中所含的杂质扩散到上覆的低杂质浓度层中，从而实现了超陡逆向沟道轮廓。

公开(公告)号：US06395606B1

公开(公告)日：2002-05-28

申请号：US09357918

申请日：1999-07-21

申请人： Carl R. Huster ,  Ognjen Milic-Strkalj ,  Emi Ishida

发明人： Carl R. Huster ,  Ognjen Milic-Strkalj ,  Emi Ishida

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66553

摘要： A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a nitride layer exposing the substrate, and performing a channel implant. A thin gate oxide layer is then thermally grown on the exposed portion of the substrate, and a relatively thin polysilicon layer is deposited on the gate oxide layer and the spacers. A metal layer, such as tungsten, is then deposited filling the opening, and planarized, as by chemical-mechanical polishing, using the nitride layer as a polish stop. Source/drain regions are thereafter formed by ion implantation, and the source/drain regions are silicided. The sidewall spacers and the nitride layer block the channel implant from the source/drain areas, thereby reducing parasitic junction capacitance, and the metal layer extending from above the gate oxide layer to the top of the gate reduces gate resistance, thereby increasing the switching speed of the finished device.

摘要翻译： 形成具有降低的寄生结电容和减小的栅极电阻的MOS半导体器件。 实施例包括在露出衬底的氮化物层中的开口的侧表面上形成氧化物侧壁间隔物，以及执行沟道植入。 然后在衬底的暴露部分上热生长薄的栅极氧化物层，并且在栅极氧化物层和间隔物上沉积相对薄的多晶硅层。 然后沉积诸如钨的金属层，填充开口，并且通过化学机械抛光使用氮化物层作为抛光停止来平坦化。 之后通过离子注入形成源极/漏极区，并且源/漏区被硅化。 侧壁间隔物和氮化物层阻挡从源极/漏极区域的沟道注入，由此减小寄生结电容，并且从栅极氧化物层上方延伸到栅极顶部的金属层降低栅极电阻，从而增加开关速度 的成品设备。

公开(公告)号：US06355528B1

公开(公告)日：2002-03-12

申请号：US09426911

申请日：1999-10-26

申请人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

发明人： Emi Ishida ,  Scott Luning ,  Tim Thurgate

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28141 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  Y10S438/947

摘要： A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

摘要翻译： 在衬底上形成窄槽。 为了形成这样的窄槽，在基板上形成第一材料，第一材料具有侧壁。 形成邻接侧壁的间隔物。 随后，与间隔物相邻地形成第二材料。 去除间隔物，留下第一材料和第二材料之间的凹槽。 在一个实施例中，槽被填充用于诸如门的窄特征的材料，并且第一材料和第二材料被去除。 结果，形成具有由间隔物的宽度限定的长度的门或其他窄特征。 在另一个实施例中，通过小凹槽执行植入物，导致小的局部植入物。

公开(公告)号：US06245623B1

公开(公告)日：2001-06-12

申请号：US09187431

申请日：1998-11-06

申请人： Dong-Hyuk Ju ,  Emi Ishida

发明人： Dong-Hyuk Ju ,  Emi Ishida

IPC分类号： H01L218236

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823814

摘要： A CMOS semiconductor device having shallow source/drain junctions is formed by ion implanting antimony to form lightly doped source/drain regions of an N-channel transistor, thereby reducing channeling for a shallower projected junction depth as compared to conventional N-type impurity implantations. Upon growing a thermal oxide screen layer to protect the substrate from subsequent ion implantations, the implanted antimony experiences oxidation-retarded diffusion, further reducing the projected junction depth. After ion implanting N-type impurities to form moderately or heavily doped source/drain regions and activation annealing, the resulting semiconductor device exhibits the desirably shallow LDD junctions.

摘要翻译： 具有浅源极/漏极结的CMOS半导体器件通过离子注入锑形成，以形成N沟道晶体管的轻掺杂源极/漏极区域，从而与传统的N型杂质注入相比减少了较浅的投影结深度的沟道。 当生长热氧化物屏幕层以保护衬底免于随后的离子注入时，注入的锑经历氧化延迟扩散，进一步降低了投影的结深度。 在离子注入N型杂质以形成适度或重掺杂的源极/漏极区域和激活退火之后，所得的半导体器件表现出期望的浅的LDD结。

公开(公告)号：US5904575A

公开(公告)日：1999-05-18

申请号：US799153

申请日：1997-02-14

申请人： Emi Ishida ,  Xiao-Yu Li ,  Sunil D. Mehta

发明人： Emi Ishida ,  Xiao-Yu Li ,  Sunil D. Mehta

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/316 ,  H01L21/8234 ,  H01L27/115 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/0231 ,  H01L21/02312 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/31662 ,  H01L21/823462 ,  H01L27/115 ,  Y10S148/126 ,  Y10S438/981

摘要： A method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting compound; applying laser energy to at least a first portion of the substrate; and forming the oxide on the surface of the substrate by heating the substrate. In a further aspect of the invention, the method comprises applying laser energy through a patterned, reflective reticle. Alternatively, prior to the step of placing, a reflective mask layer may be applied to the surface of the semiconductor substrate. In addition, the invention comprises an EEPROM memory cell having a program junction region in a semiconductor substrate. The cell comprises at least a first program junction provided in the silicon substrate and a floating gate having a portion positioned over the program junction. In addition, an oxide layer is positioned between the program junction and the floating gate, the gate oxide formed by a single thermal oxidation step to have at least a first oxide thickness and a second oxide thickness due to gas immersion laser doped nitrogen underlying a region of the oxide having said at least first oxide thickness.

摘要翻译： 一种在半导体衬底的表面上形成氧化物的方法。 该方法包括以下步骤：将半导体衬底放置在含有氧化物生长抑制化合物气氛的气氛中; 将激光能量施加到所述衬底的至少第一部分; 以及通过加热衬底在衬底的表面上形成氧化物。 在本发明的另一方面，该方法包括通过图案化的反射光罩施加激光能量。 或者，在放置步骤之前，可以将反射掩模层施加到半导体衬底的表面。 此外，本发明包括一个在半导体衬底中具有编程结区的EEPROM存储单元。 该单元包括设置在硅衬底中的至少第一程序段和具有位于程序结上方的部分的浮动栅极。 此外，氧化物层位于程序结和浮置栅极之间，栅极氧化物通过单个热氧化步骤形成，以由于气体浸没激光掺杂氮在下面的区域具有至少第一氧化物厚度和第二氧化物厚度 的具有所述至少第一氧化物厚度的氧化物。

公开(公告)号：US06455385B1

公开(公告)日：2002-09-24

申请号：US09003751

申请日：1998-01-07

申请人： Roger L. Alvis ,  Emi Ishida

发明人： Roger L. Alvis ,  Emi Ishida

IPC分类号： H01L21265

CPC分类号： H01L29/78 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324

摘要： A method of reducing implant dose loss is provided. The method includes performing multiple low dose implant steps with interspersed anneal steps, thereby avoiding amorphous-silicon formation. The anneal steps may be performed at high temperatures or at low temperatures.

摘要翻译： 提供减少植入剂量损失的方法。 该方法包括执行具有散置退火步骤的多个低剂量注入步骤，从而避免非晶硅形成。 退火步骤可以在高温或低温下进行。

公开(公告)号：US06423601B1

公开(公告)日：2002-07-23

申请号：US09667685

申请日：2000-11-14

申请人： Emi Ishida ,  Ming Yin Hao

发明人： Emi Ishida ,  Ming Yin Hao

IPC分类号： H01L21336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/823814 ,  H01L29/6659

摘要： Submicron-dimensioned, p-channel MOS transistors and CMOS devices a formed using nitrogen and boron co-implants for forming p-type well regions, each implant having a parabolically-shaped concentration distribution profile. During subsequent thermal annealling, boron-doped wells are formed, each having a retrograde-shaped concentration distribution profile exhibiting a peak boron concentration at a preselected depth below the semiconductor substrate surface. The inventive method reduces “short-channel” effects such as “punch-through” while maintaining high channel mobility.

摘要翻译： 使用用于形成p型阱区的氮和硼共注入物形成的亚微米尺寸的p沟道MOS晶体管和CMOS器件a，每个植入物具有抛物线形的浓度分布曲线。 在随后的热退火期间，形成硼掺杂的阱，每个具有在半导体衬底表面下方的预选深度处呈现峰值硼浓度的逆向浓度分布分布。 本发明的方法在保持高信道移动性的同时减少了“短通道”效应，例如“穿透”。

公开(公告)号：US06410393B1

公开(公告)日：2002-06-25

申请号：US09639797

申请日：2000-08-17

申请人： Ming-Yin Hao ,  Emi Ishida

发明人： Ming-Yin Hao ,  Emi Ishida

IPC分类号： H01L21336

CPC分类号： H01L29/66659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/7835

摘要： Short channel effects are curtailed thereby increasing integrated circuit speed by forming a channel dopant with an asymmetric impurity concentration profile. Embodiments include ion implanting Si or Ge at a large tilt angle to amorphize a portion of a designated channel region with a varying degree of amorphization decreasing from the intended drain region to the intended source region, substantially vertically ion implanting channel dopant impurities and annealing. During annealing, diffusion is retarded in areas of increased amorphization, thereby forming an asymmetric impurity concentration gradient across the channel region increasing in the direction of the source region.

摘要翻译： 缩短通道效应，从而通过形成具有不对称杂质浓度分布的沟道掺杂剂来提高集成电路速度。 实施例包括以大的倾斜角度离子注入Si或Ge，以使指定通道区域的一部分非晶化，其中不同程度的非晶化从预期的漏极区域到预期的源极区域，基本上垂直离子注入沟道掺杂剂杂质和退火。 在退火过程中，在非晶化过程增大的区域中扩散被延迟，从而在源极区域的方向上跨越沟道区域形成不对称杂质浓度梯度。