公开(公告)号：US06265291B1

公开(公告)日：2001-07-24

申请号：US09224754

申请日：1999-01-04

Applicant: Bin Yu ,  Emi Ishida

Inventor： Bin Yu ,  Emi Ishida

IPC: H01L2104

CPC classification number: H01L21/28518 ,  H01L21/26506

Abstract: A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.

Abstract translation: 本文公开了制造用于优化杂质扩散层和硅化物之间的接触电阻的集成电路的方法。 该方法包括将第一材料注入到半导体层中以产生埋入的非晶硅层; 将第二材料注入到半导体层和埋入非晶层中，形成具有弯曲形状的掺杂剂分布区域; 在半导体层上沉积金属层; 熔化埋入的非晶层以将弯曲形状重新配置为最大掺杂剂浓度的基本垂直分布; 并且用半导体层和金属层形成硅化物，硅化物的底部位于掺杂物分布区域上的垂直形状。

公开(公告)号：US06403433B1

公开(公告)日：2002-06-11

申请号：US09397217

申请日：1999-09-16

Applicant: Bin Yu ,  Jonathan Kluth ,  Emi Ishida

Inventor： Bin Yu ,  Jonathan Kluth ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/78618

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.

Abstract translation: 超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括升高的源极和漏极区域。 在掺杂之前，升高的源极和漏极区非晶化。 中性离子物质可用于使提升的源极和漏极区域非晶化。 掺杂剂在低温快速热退火工艺中被激活。

公开(公告)号：US06190980B1

公开(公告)日：2001-02-20

申请号：US09150874

申请日：1998-09-10

Applicant: Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

Inventor： Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/66537

Abstract: A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

Abstract translation: 在ULSI致密结构中进行凹槽，晕圈和源极/漏极延伸的倾斜注入的方法。 该方法克服了在密集结构中的阴影效应，在ULSI电路中使用大角度倾斜植入技术的过程极限。 通过插入氮化物间隔物限定氧化层中的开口，并且通过插入氮化物间隔物来部分地填充以限定实际的门窗开口。 小角度倾斜植入技术具有大角度倾斜植入物的等效掺杂效应，并避开了大角度植入法中发生的最大角度限制（thetaMAX）。 小角度倾斜植入技术还自动提供袋/晕/延伸植入物到装置的门的自对准。

公开(公告)号：US06180468B2

公开(公告)日：2001-01-30

申请号：US09177774

申请日：1998-10-23

Applicant: Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

Inventor： Bin Yu ,  Emi Ishida ,  Scott Luning ,  Timothy Thurgate

IPC: H01L21336

CPC classification number: H01L29/66537 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

Abstract: An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate is removed, a nitride film deposition and etch is used to form a nitride spacer with a predetermined configuration, and a self-aligned channel implant is performed. After the channel implantation, anneal and super-retrograded doping, the nitride spacer and the gate oxide are removed for subsequent regrowth of a second gate oxide and a polysilicon deposition to form a second polysilicon gate.

Abstract translation: 通过使用反向工艺流程为通道注入提供超低热量预算过程，其中形成常规MOS晶体管而不需要沟道注入。 去除原来沉积的多晶硅栅极，使用氮化物膜沉积和蚀刻来形成具有预定配置的氮化物间隔物，并且执行自对准沟道注入。 在通道注入，退火和超退火掺杂之后，去除氮化物间隔物和栅极氧化物，以便随后的第二栅极氧化物的再生长和多晶硅沉积形成第二多晶硅栅极。

公开(公告)号：US20070112176A1

公开(公告)日：2007-05-17

申请号：US10551780

申请日：2004-04-02

Applicant: Motoharu Seiki ,  Ikuo Yana ,  Takanori Aoki ,  Junko Yasuda ,  Hiroshi Kikuchi ,  Emi Ishida

Inventor： Motoharu Seiki ,  Ikuo Yana ,  Takanori Aoki ,  Junko Yasuda ,  Hiroshi Kikuchi ,  Emi Ishida

IPC: A61K9/127 ,  C07K14/82

CPC classification number: A61K31/704 ,  A61K9/127 ,  A61K47/6871 ,  A61K47/6901 ,  A61K48/00

Abstract: A lipid membrane structure containing an anti-membrane-type matrix metalloproteinase monoclonal antibody such as an anti-MT1-MMP monoclonal antibody as a component of the lipid membrane structure. Said structure can be utilized as a drug delivery system for efficiently delivering a medicinally active ingredient and/or a gene to tumor cells, neoplastic vessel and the like in which a membrane-type matrix metalloproteinase (MT-MMP) is expressed.

Abstract translation: 含有抗 - 膜型基质金属蛋白酶单克隆抗体如抗MT1-MMP单克隆抗体作为脂质膜结构的组分的脂质膜结构。 所述结构可用作药物递送系统，用于向其中表达膜型基质金属蛋白酶（MT-MMP）的肿瘤细胞，肿瘤血管等有效递送药物活性成分和/或基因。

公开(公告)号：US06642134B2

公开(公告)日：2003-11-04

申请号：US09401797

申请日：1999-09-22

Applicant: Emi Ishida ,  Scott Luning

Inventor： Emi Ishida ,  Scott Luning

IPC: H01L213205

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/823864 ,  H01L29/6656

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract translation: 半导体器件设置有用于形成源极/漏极区域的半导体侧壁间隔物。 半导体侧壁间隔物还减少了通过浅源极/漏极结的自杀性短路的可能性。 实施例包括掺杂半导体侧壁间隔物，使得它们用作在激活退火期间形成源极/漏极延伸的杂质源。

公开(公告)号：US06277698B1

公开(公告)日：2001-08-21

申请号：US09382580

申请日：1999-08-25

Applicant: Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

Inventor： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/823842

Abstract: A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.

Abstract translation: 通过在沉积栅极电极层之前形成电介质膜，半导体器件设置有具有大致矩形轮廓的栅电极。 对电介质膜进行图案化和蚀刻以形成具有由开放区域分开的矩形轮廓的区域。 然后沉积栅极电极层，然后平坦化以形成具有基本上矩形轮廓的栅电极。

公开(公告)号：US6143632A

公开(公告)日：2000-11-07

申请号：US993049

申请日：1997-12-18

Applicant: Emi Ishida ,  Peng Fang

Inventor： Emi Ishida ,  Peng Fang

IPC: H01L21/265 ,  H01L21/28 ,  H01L29/32 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/32 ,  H01L29/4983 ,  H01L29/518

Abstract: A semiconductor device having reduced hot carrier degradation is achieved by doping the semiconductor substrate and gate oxide with deuterium. A conventional semiconductor device is formed with sequentially deposited metal layers and dielectric layers and a topside protective dielectric layer deposited thereon. Deuterium is introduced to the semiconductor device by using deuterium-containing reactants in at least one of the semiconductor manufacturing steps to passivate dangling silicon bonds at the silicon/oxide interface region.

Abstract translation: 具有减少的热载流子劣化的半导体器件通过用氘掺杂半导体衬底和栅极氧化物来实现。 常规的半导体器件形成有顺序沉积的金属层和介电层以及沉积在其上的顶侧保护电介质层。 通过在半导体制造步骤中的至少一个中使用含氘的反应物，在硅/氧化物界面区域钝化悬挂的硅键，将氘引入半导体器件。

公开(公告)号：US5885904A

公开(公告)日：1999-03-23

申请号：US799235

申请日：1997-02-14

Applicant: Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

Inventor： Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

IPC: H01L21/311 ,  H01L21/316 ,  H01L21/461 ,  H01L21/31

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/0231 ,  H01L21/02312 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31662

Abstract: A method for forming a uniform and reliable oxide layer on the surface of a semiconductor substrate using projection gas immersion laser doping (P-GILD) is provided. A semiconductor substrate is immersed in an oxide enhancing compound containing atmosphere. The oxide enhancing compound containing atmosphere may include phosphorus, arsenic, boron or an equivalent. A 308 nm excimer laser is then applied to a portion of the substrate to induce incorporation of the oxide enhancing compound into a portion of the substrate. The deposition depth is dependent upon the strength of the laser energy directed at the surface of the substrate. A uniform and reliable oxide layer is then formed on the surface of the substrate by heating the substrate. The laser may be applied with a reflective reticle or mask formed on the substrate. An E.sup.2 PROM memory cell having a program junction region in a silicon substrate is also provided. An oxide layer is positioned between a program junction and a floating gate. The oxide layer is formed by a single or multiple thermal oxidation step(s) to have at least a first oxide thickness due to a GILD oxide enhancing compound underlying a region of the oxide having at least the first oxide thickness.

Abstract translation: 提供了使用投影气体浸渍激光掺杂（P-GILD）在半导体衬底的表面上形成均匀且可靠的氧化物层的方法。 将半导体衬底浸入含氧化物增强化合物的气氛中。 含氧化物增强化合物的气氛可以包括磷，砷，硼或等价物。 然后将308nm准分子激光器施加到衬底的一部分以诱导氧化物增强化合物掺入衬底的一部分中。 沉积深度取决于指向衬底表面的激光能量的强度。 然后通过加热衬底在衬底的表面上形成均匀且可靠的氧化物层。 可以在基板上形成反射型掩模版或掩模来施加激光。 还提供了具有硅衬底中的程序接合区的E2PROM存储单元。 氧化物层位于程序结和浮动栅之间。 通过单个或多个热氧化步骤形成氧化物层，以至少具有第一氧化物厚度，这是由于至少具有第一氧化物厚度的氧化物区域下面的GILD氧化物增强化合物。

公开(公告)号：US06472283B1

公开(公告)日：2002-10-29

申请号：US09667787

申请日：2000-09-22

Applicant: Emi Ishida ,  Srinath Krishman ,  Ming Yin Hao ,  Effiong Ibok

Inventor： Emi Ishida ,  Srinath Krishman ,  Ming Yin Hao ,  Effiong Ibok

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract translation: 亚微米尺寸的MOS和/或CMOS晶体管通过采用由诸如UV氮化物的材料制成的可移除的侧壁间隔的工艺制造，其易于以其沉积的未增稠的状态蚀刻，但在其热 退火，致密化状态。 通过在植入中等或重掺杂的源极/漏极区域之后但在用于掺杂剂扩散/激活和晶格损伤弛豫的植入物退火之前用稀释的HF水溶液去除沉积的未增塑的间隔物。 轻微或中度掺杂的浅深度源极/漏极延伸部分在去除间隔物之后被植入和退火。