A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal.