公开(公告)号：US06278297B1

公开(公告)日：2001-08-21

申请号：US09395592

申请日：1999-09-14

申请人： Stewart M. DeSoto ,  David B. Scott

发明人： Stewart M. DeSoto ,  David B. Scott

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal.

公开(公告)号：US06426655B2

公开(公告)日：2002-07-30

申请号：US09812792

申请日：2001-03-20

申请人： Stewart M. DeSoto ,  David B. Scott

发明人： Stewart M. DeSoto ,  David B. Scott

IPC分类号： H03K19084

CPC分类号： G11C8/08

摘要： A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal

摘要翻译： 电路设计有具有第一输出端（319）的解码电路（313-315）。 解码电路被耦合以接收具有第一电压范围的地址信号（81,82,85），用于产生具有第一和第二逻辑电平之一的第一输出信号。 输出电路（307,309）被耦合以接收第一输出信号和电源信号。 输出电路产生具有第二电压范围的第二输出信号。 第一锁存晶体管（301）被耦合以接收第二输出信号。 第一锁存晶体管被布置成响应于第二输出信号的第一和第二逻辑状态之一将第一输出端子耦合到电压端子（209）。 第二锁存晶体管（317）被耦合以接收第二输出信号。 第二锁存晶体管被布置成响应于第二输出信号的第一和第二逻辑状态中的另一个而将第一输出端耦合到参考端（318）