发明授权
- 专利标题: Semiconductor device which reduces the minimum distance requirements between active areas
- 专利标题(中): 降低有效区域之间最小距离要求的半导体器件
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申请号: US08685726申请日: 1996-07-24
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公开(公告)号: US06281562B1公开(公告)日: 2001-08-28
- 发明人: Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
- 申请人: Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
- 优先权: JP7-192181 19950727; JP7-330112 19951219
- 主分类号: H01L29167
- IPC分类号: H01L29167
摘要:
An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
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