Power transistor with silicided gate and contacts

发明授权

US06284669B1 Power transistor with silicided gate and contacts 有权

标题翻译：功率晶体管采用硅化栅和触点

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专利标题： Power transistor with silicided gate and contacts
专利标题（中）： 功率晶体管采用硅化栅和触点
申请号： US09168194

申请日： 1998-10-07
公开(公告)号： US06284669B1

公开(公告)日： 2001-09-04
发明人: John P. Erdeljac , Louis N. Hutter , Jeffrey P. Smith , Han-Tzong Yuan , Jau-Yuann Yang , Taylor R. Efland , C. Matthew Thompson , John K. Arch , Mary Ann Murphy
申请人： John P. Erdeljac , Louis N. Hutter , Jeffrey P. Smith , Han-Tzong Yuan , Jau-Yuann Yang , Taylor R. Efland , C. Matthew Thompson , John K. Arch , Mary Ann Murphy
主分类号： H01L21302
IPC分类号： H01L21302

Power transistor with silicided gate and contacts

摘要：

A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).

摘要（中）：

公开了一种功率场效应晶体管，其包括分别设置在主体（40）和（42）的外表面上的铂硅化物接触层（74）和（78）的多晶硅栅极体（40）和（42）。另外，该器件还包括在其外表面上形成有铂硅化物漏极接触层（76）和铂硅化物源极接触层（75）和（77）的n +漏极区域（64）。在形成期间，侧壁间隔物（50）和（52）以及掩模体（70）和（72）用于确保与两个闸门体（40）和（42）间隔开的铂硅化物层（76）和铂硅化物栅极接触层（74）和（78）。

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