公开(公告)号：US6008519A

公开(公告)日：1999-12-28

申请号：US990549

申请日：1997-12-15

申请人： Han-Tzong Yuan ,  Donald L. Plumpton ,  Jau-Yuann Yang ,  Tae S. Kim

发明人： Han-Tzong Yuan ,  Donald L. Plumpton ,  Jau-Yuann Yang ,  Tae S. Kim

IPC分类号： H01L21/335 ,  H01L29/772 ,  H01L29/76 ,  H01L29/74 ,  H01L29/80

CPC分类号： H01L29/66416 ,  H01L29/7722

摘要： A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).

摘要翻译： 一种包括第一导电类型的第一半导体层（14）的垂直晶体管（70）。 设置在第一半导体层（14）上的第二导电类型的栅极结构（32）。 栅极结构（32）可以包括由通道（40）分开的多个栅极（38）。 第一导电类型的第二半导体层（50）可以设置在栅极结构（32）上和通道（40）中。 止动元件（36）可以设置在栅极（38）和第二半导体层（50）的上表面之间。 可以在栅极（38）上的第二半导体层（50）中形成空穴（52）。

公开(公告)号：US5548141A

公开(公告)日：1996-08-20

申请号：US441847

申请日：1995-05-16

申请人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

发明人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L29/161

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  Y10S148/011 ,  Y10S148/072

摘要： A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

摘要翻译： 自发对准发射极接触的方法包括在集电极层（16）的一部分上形成基极层（18）。 界面层（22）形成在基底层（18）上，使得基底层（18）的一部分保持暴露。 发射极层（24）形成在集电层（16），界面层（22）和基层（18）的露出部分上。 在基底层（18）的预先暴露的区域上的发射极层（24）上形成发射极覆盖层（26）。 绝缘层（28）形成在界面层（22）上。 在基底层（18）的预先暴露的区域处，在发射极盖层（26）上形成发射极触点（36）。 绝缘层（28）将发射极触点（36）与基底层（18）和随后形成的基部触点（38）隔离开来。 绝缘层（28）确保发射极触点（36）和基极触点（38）之间的隔离，尽管发射极触点（36）在形成期间未对准。

公开(公告)号：US5420052A

公开(公告)日：1995-05-30

申请号：US230357

申请日：1994-04-19

申请人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

发明人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  Y10S148/072

摘要： A method of fabricating a semiplanar heterojunction bipolar transistor (10) includes forming a subcollector layer (12) and a collector layer (16) onto a substrate layer (14). A collector implant plug (18) is selectively implanted to connect the subcollector layer (12) to the surface of the heterojunction bipolar transistor (10). A second epitaxial growth process causes a base layer (22), an emitter layer (24), and an emitter cap layer (26) to form on the collector layer (16) and the collector implant plug (18). By this process, the base layer (22) is not exposed to subsequent harmful fabrication steps. A base plug region (28) is selectively implanted to connect the base layer (22) to the surface of the heterojunction bipolar transistor (10). A base contact (32) and an emitter contact (30) are selectively formed within the heterojunction region on the base plug region (28) and the emitter cap layer (26), respectively. Lateral parasitic diodes between the base contact (32) and the emitter contact (30) are etched away to isolate the base contact (32) from the emitter contact (30). The emitter cap layer (26), the emitter layer (24), and the base layer (22) are removed from the vicinity of the collector implant plug (18) to allow formation of the collector contact (34).

摘要翻译： 制造半平面异质结双极晶体管（10）的方法包括在衬底层（14）上形成子集电极层（12）和集电极层（16）。 选择性地注入集电极注入插头（18）以将子集电极层（12）连接到异质结双极晶体管（10）的表面。 第二外延生长工艺使得在集电极层（16）和集电极植入插头（18）上形成基极层（22），发射极层（24）和发射极盖层（26）。 通过该过程，基层（22）不暴露于随后的有害制造步骤。 选择性地注入基座区域（28）以将基极层（22）连接到异质结双极晶体管（10）的表面。 基极触点（32）和发射极触点（30）分别选择性地形成在基插塞区域（28）和发射极盖层（26）上的异质结区域内。 基极触点（32）和发射极触点（30）之间的侧向寄生二极管被蚀刻掉以将基极触点（32）与发射极触点（30）隔离。 发射极帽层（26），发射极层（24）和基底层（22）从集电极植入插头（18）的附近被去除，以形成集电极触点（34）。

公开(公告)号：US5231037A

公开(公告)日：1993-07-27

申请号：US876252

申请日：1992-04-30

申请人： Han-Tzong Yuan ,  Tae S. Kim ,  Francis J. Morris

发明人： Han-Tzong Yuan ,  Tae S. Kim ,  Francis J. Morris

IPC分类号： H01L29/80 ,  H01L21/335 ,  H01L21/337 ,  H01L29/207 ,  H01L29/772

CPC分类号： H01L29/66454 ,  H01L29/207 ,  H01L29/66924 ,  H01L29/7722 ,  Y10S148/04

摘要： This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

公开(公告)号：US5053346A

公开(公告)日：1991-10-01

申请号：US495951

申请日：1990-03-20

申请人： Han-Tzong Yuan ,  Liem Th Tran

发明人： Han-Tzong Yuan ,  Liem Th Tran

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/7327 ,  H01L29/7371 ,  Y10S148/011

摘要： Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced. This in turn reduces the capacitance associated with this junction and correspondingly improves device operating speed. By forming a portion of the collector in the trench, the lateral dimensions of the transistor may be reduced and higher levels of device integration are made possible.

摘要翻译： 在砷化镓衬底中制造具有大大降低的发射极到基极结面积和集电极尺寸的垂直埋地发射极异质结双极晶体管，以形成集成电路结构。 通过沿着已经在层状砷化镓结构的上两层中蚀刻的沟槽的侧壁和底部形成基底的一部分来实现缩放这些临界尺寸的能力。 基底通过将铍注入上层的表面，形成在未掺杂层中的沟槽侧壁和形成在掩埋发射体上的未掺杂层的沟槽的底部而形成。 具有减小的横向尺寸的GaAs集电极层沉积在沟槽中并且部分地沉积在分层结构的表面上。 由于基极区域的一小部分（沟槽的底部）与重掺杂的发射极层直接接触，所以发射极到基极结面积可以显着降低。 这反过来又降低了与该结点相关联的电容，并相应地提高了器件的工作速度。 通过在沟槽中形成集电极的一部分，可以减小晶体管的横向尺寸，使得可以实现更高水平的器件集成。

公开(公告)号：US4654960A

公开(公告)日：1987-04-07

申请号：US808901

申请日：1985-12-13

申请人： William V. McLevige ,  Han-Tzong Yuan ,  Walter M. Duncan ,  Friedrich H. Doerbeck

发明人： William V. McLevige ,  Han-Tzong Yuan ,  Walter M. Duncan ,  Friedrich H. Doerbeck

IPC分类号： H01L21/76 ,  H01L27/02 ,  H01L29/732 ,  H01L21/265 ,  H01L29/48

CPC分类号： H01L27/0233 ,  H01L21/7605 ,  H01L27/024 ,  H01L29/7327 ,  Y10S148/084

摘要： Bipolar transistors and other electronic structures are fabricated on a gallium arsenide (GaAs) substrate to form an integrated circuit device. This process is made possible by development of an ion implant technique which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. The process avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with the ion implant method, makes possible the fabrication of IC quality transistors consistently over a substrate. This same control enables the fabrication of integrated circuits with improved device packing density and reduced parasitic parameters.

摘要翻译： 在砷化镓（GaAs）衬底上制造双极晶体管和其它电子结构以形成集成电路器件。 通过开发使用受主材料以产生P型区域，硼或质子以产生绝缘区域以及硅或硒以产生N型区域的离子注入技术，可以实现该过程。 该过程避免了扩散方法中遇到的困难问题，并且由于采用离子注入方法可以进行精确的控制，使得可以在衬底上一致地制造IC质量晶体管。 该相同的控制使得能够制造具有改进的装置堆积密度和减小的寄生参数的集成电路。

公开(公告)号：US06627507B2

公开(公告)日：2003-09-30

申请号：US09740884

申请日：2000-12-21

申请人： Han-Tzong Yuan

发明人： Han-Tzong Yuan

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01L23/66 ,  H01L27/0629 ,  H01L27/08 ,  H01L27/12 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention relates to an improved substrate (100) using a layer (112) or region (130) of porous silicon that is created in the bulk silicon substrate material (110) to increase the resistivity of the substrate (100) thus making it suitable for passive component integration directly on the motherboard (200) or chip (230) and useful for high frequency applications due to its low loss, low dielectric properties. One or more passive components such as inductors (214), resistors (212) and capacitors (216) can be integrated on the device (140) over the porous silicon region (130). The high resistivity of the device makes it ideal for integration on a single platform using conventional wafer fab processes since loss at radio frequencies is comparably less when compared to a pure silicon substrate.

公开(公告)号：US06297515B1

公开(公告)日：2001-10-02

申请号：US09393777

申请日：1999-09-10

申请人： Han-Tzong Yuan

发明人： Han-Tzong Yuan

IPC分类号： H01L2978

CPC分类号： H03H9/175 ,  H03B5/30

摘要： An resonator circuit and an integrated circuit including the resonator circuit and method of making. A silicon substrate of a first conductivity type (1) is provided and an integrated circuit TFR circuit (23) is formed on a region of the substrate which includes a stack containing a plurality of alternately non-porous (3,7,11) silicon and porous (5,9,13) silicon layers. A method is provided to deposit layers with alternately opposite conductivity type and convert only one conductivity type but not the other into porous silicon materials. Each of these layers generally has the thickness which is one quarter of an acoutic wavelength of the resonator frequency. A noise isolator (17,19) is disposed along the sidewalls of the stack and extends into the substrate. A region of silicon (29) is disposed on the substrate and separated from the reflector by the noise isolator. At least one of an active and/or passive device (27) is disposed on or in said region of silicon. There can additionally or alternatively be at least one passive device disposed over the noise isolator (25) with an interconnect (21) interconnecting the resonator and the at least one of an active and/or passive device and the at least one passive device. The noise isolator can completely surrounds the stack. The noise isolator is preferably porous silicon.

摘要翻译： 谐振器电路和包括谐振器电路和制造方法的集成电路。 提供第一导电类型（1）的硅衬底，并且在衬底的区域上形成集成电路TFR电路（23），该集成电路包括多个交替无孔（3,7,11）硅 和多孔（5,9,13）硅层。 提供了一种方法来沉积具有交替相反导电类型的层，并且仅将一种导电类型而不是另一种转化为多孔硅材料。 这些层中的每一个通常具有的是谐振器频率的四分之一波形的厚度。 噪声隔离器（17,19）沿着堆叠的侧壁设置并延伸到衬底中。 硅（29）的区域设置在基板上并且通过噪声隔离器与反射器分离。 有源和/或无源器件（27）中的至少一个设置在硅的所述区域上或其中。 另外还可以是至少一个设置在噪声隔离器（25）上的无源器件，其中互连（21）将谐振器和有源和/或无源器件和至少一个无源器件中的至少一个互连。 噪声隔离器可以完全围绕堆叠。 噪声隔离器优选为多孔硅。

公开(公告)号：US5909110A

公开(公告)日：1999-06-01

申请号：US989840

申请日：1997-12-12

申请人： Han-Tzong Yuan ,  Albert H. Taddiken ,  Donald L. Plumton ,  Jau-Yuann Yang

发明人： Han-Tzong Yuan ,  Albert H. Taddiken ,  Donald L. Plumton ,  Jau-Yuann Yang

IPC分类号： G05F1/56 ,  G05F1/40

CPC分类号： G05F1/56

摘要： A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

摘要翻译： 一种包括垂直沟道晶体管（12）的电压调节器（10）。 垂直沟道晶体管（12）可以具有栅极（16），电压输入端子（18）和电压输出端子（20）。 参考电压源（14）可以耦合到栅极（16）。

公开(公告)号：US5822473A

公开(公告)日：1998-10-13

申请号：US808816

申请日：1997-02-28

申请人： Gregory Anton Magel ,  Terrance Gus McDonald ,  Jau-Yuann Yang ,  Han-Tzong Yuan

发明人： Gregory Anton Magel ,  Terrance Gus McDonald ,  Jau-Yuann Yang ,  Han-Tzong Yuan

IPC分类号： G01N21/77 ,  G02B6/12 ,  G02B6/26

CPC分类号： G01N21/7703 ,  G02B6/12004

摘要： An optical device for sensing properties in an environment such as the presence of a substance or chemical in the zone to be monitored using optical components integrated on a microchip base or substrate. A preferred embodiment introduces a method for fabricating a miniature microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 48 and a silicon photosensor 16 on the same chip. Light 18 is emitted at the edge of the GaAs LED 14. A portion of the light propagates is detected by a PIN diode 16. A chemical sensitive material 50 is coated on top of a polyimide waveguide 48. When the gas or chemical to which the material is sensitive appears, the light transmitted from the polyimide to air increases, thus the total signal sensed by the photodetector decreases, whereby the change in light signal indicates detection.

摘要翻译： 一种光学装置，用于使用集成在微芯片基座或基板上的光学元件在诸如物体或化学物质存在的环境中感测特性。 优选实施例通过在同一芯片上集成GaAs LED 14与聚酰亚胺波导48和硅光电传感器16来引入制造微型微芯片化学传感器的方法。 灯18在GaAs LED 14的边缘处发射。一部分光传播由PIN二极管16检测。化学敏感材料50涂覆在聚酰亚胺波导48的顶部。当气体或化学物质 材料敏感出现，从聚酰亚胺向空气传播的光线增加，光电探测器感测到的总信号减小，光信号变化表示检测。