A flash memory device (100) includes a core cell array including two banks (194, 196) of core cells and address decoding circuitry (112, 114, 118, 120) and a write protect circuit. The write protect circuit includes sector write protect circuits (210) associated with respective sectors (202) of the core cell array in storing write protect data for the associated sector. The write protect circuit further includes a switch circuit (404) which selects one sector write protect signal in response to a write select signal to produce a combined write protect signal. The write protect circuit further includes an output circuit (406) coupled to the switch circuit to produce a sector write protect signal.