公开(公告)号：US06957297B1

公开(公告)日：2005-10-18

申请号：US10603136

申请日：2003-06-23

申请人： Lee E. Cleveland ,  Kendra Nguyen

发明人： Lee E. Cleveland ,  Kendra Nguyen

IPC分类号： G11C16/10 ,  G11C16/26 ,  G06F12/02

CPC分类号： G11C16/26 ,  G11C16/10 ,  G11C2216/22

摘要： A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.

摘要翻译： 一种用于操作闪速存储器的方法包括：响应于所接收的操作命令，启动闪速存储器的嵌入式操作，随后在执行嵌入式操作期间，响应于接收到的读取命令，启动闪存读取操作 闪存

公开(公告)号：US07284167B2

公开(公告)日：2007-10-16

申请号：US11041608

申请日：2005-01-24

申请人： Mimi Lee ,  Darlene Hamilton ,  Ken Cheong Cheah ,  Kendra Nguyen ,  Xin Guo

发明人： Mimi Lee ,  Darlene Hamilton ,  Ken Cheong Cheah ,  Kendra Nguyen ,  Xin Guo

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/021 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/16

摘要： A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.

摘要翻译： 讨论了一种用于为闪存设备的内置自测电路提供可编程测试条件的方法。 该方法包括提供BIST接口，其适于调整在BIST电路中使用的测试条件，提供闪存设备的存储单元，以及提供适于测试闪速存储器的BIST电路。 该方法还包括与BIST接口通信与测试条件相关联的一个或多个全局变量，基于由全局变量表示的值来调整由BIST电路使用的测试条件，对闪速存储器执行一个或多个测试操作 根据调整的测试条件，并记录测试操作的结果。 本发明的方法还可以包括串行通信介质和使用串行测试协议来将全局变量传送到BIST接口并从接口测试结果。 全局变量也可由存储器设备用户提供。

公开(公告)号：US06654848B1

公开(公告)日：2003-11-25

申请号：US09662791

申请日：2000-09-15

申请人： Lee E. Cleveland ,  Kendra Nguyen

发明人： Lee E. Cleveland ,  Kendra Nguyen

IPC分类号： G06F1200

CPC分类号： G11C16/26 ,  G11C16/10 ,  G11C2216/22

摘要： A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.

摘要翻译： 一种用于操作闪速存储器的方法包括：响应于所接收的操作命令，启动闪速存储器的嵌入式操作，随后在执行嵌入式操作期间，响应于接收到的读取命令，启动闪存读取操作 闪存

公开(公告)号：US06351420B1

公开(公告)日：2002-02-26

申请号：US09595519

申请日：2000-06-16

申请人： Takao Akaogi ,  Ali K. Al-Shamma ,  Lee Edward Cleveland ,  Yong Kim ,  Jin-Lien Lin ,  Boon Tang Teh ,  Kendra Nguyen

发明人： Takao Akaogi ,  Ali K. Al-Shamma ,  Lee Edward Cleveland ,  Yong Kim ,  Jin-Lien Lin ,  Boon Tang Teh ,  Kendra Nguyen

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C16/12 ,  G11C16/30

摘要： A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

摘要翻译： 用于闪存（100）的升压电路（111）包括升压电路（110），其能够将闪存的电源电压（VCC）的一部分升压到足以访问的字线电压电平 存储器的核心单元阵列（102）中的核心单元。 升压电路还包括用于向升压电路提供非零调节电压（VCL）的平衡或钳位电路（112），以在电源电压超过时减小升压电路可用于升压的电源电压部分 一定的价值。

公开(公告)号：US20090273498A1

公开(公告)日：2009-11-05

申请号：US12114693

申请日：2008-05-02

申请人： Dimitry Goder ,  Zongqi Hu ,  Kendra Nguyen

发明人： Dimitry Goder ,  Zongqi Hu ,  Kendra Nguyen

IPC分类号： H03M1/12

CPC分类号： H02M3/157 ,  H02M3/1584 ,  H02M2001/0009

摘要： A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.

摘要翻译： 开关电压调节器部分地包括N个输出级，环路ADC，多路复用器，电流ADC和中断块。 环路模数转换器接收N个输出电压，每个N个输出电压与N个通道中的一个相关联。 环路ADC适于改变每个施加到产生N个输出电压的N个输出级中的一个的N个信号的占空比。 如果在至少两个采样时间期间在输出级感测的电压之间的差超过预定义的阈值，则中断块适于使多路复用器将输出级耦合到当前ADC。 如果在输出级感测的电压与参考电压之间的差超过预定义的阈值，则中断块还可以适于使多路复用器将输出级耦合到当前ADC模块。

公开(公告)号：US06621761B2

公开(公告)日：2003-09-16

申请号：US09829518

申请日：2001-04-09

申请人： Takao Akaogi ,  Lee Cleveland ,  Kendra Nguyen

发明人： Takao Akaogi ,  Lee Cleveland ,  Kendra Nguyen

IPC分类号： G06C800

CPC分类号： G11C7/1018 ,  G11C7/1072

摘要： A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit, a control circuit coupled to the first circuit, and a data buffer selectively coupled to the first circuit by the control circuit. The first circuit accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal. The data buffer has an output and produces the first data word at the output and successively produces, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output. The subsequent data words correspond to the subsequent accesses of the plurality of data words.

公开(公告)号：US06347052B1

公开(公告)日：2002-02-12

申请号：US09690554

申请日：2000-10-17

申请人： Takao Akaogi ,  Ali K. Al-Shamma ,  Lee Cleveland ,  Yong Kim ,  Jin-Lien Lin ,  Kendra Nguyen ,  Boon Tang Teh

发明人： Takao Akaogi ,  Ali K. Al-Shamma ,  Lee Cleveland ,  Yong Kim ,  Jin-Lien Lin ,  Kendra Nguyen ,  Boon Tang Teh

IPC分类号： G11C1606

CPC分类号： G11C16/08 ,  G11C8/10

摘要： A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.

摘要翻译： 描述了具有字线解码和选择架构的闪速存储器。 闪速存储器包括存储单元的第一和第二扇区，第一和第二本地驱动电路，第一，第二和第三解码电路以及驱动电路。 第一存储器单元的第一扇区包括耦合到第一存储器单元的第一多个字线，每个字线能够是第一选定的字线。 第二存储器单元的第二扇区包括类似的局部驱动器电路独立地耦合到第一扇区的第一和第二多个字线的每个字线。 每个解码电路包括解码电路的第一和第二侧。 解码电路的第一侧激活第一选定的多个本地驱动器电路，并且解码电路的第二侧激活第二选定的多个局部驱动器电路。 第二解码电路耦合到第一本地驱动电路，并将第一升压电压提供给耦合到第一本地驱动电路的第一选定字线。 第三解码电路耦合到第二本地驱动电路，并将第二升压电压提供给第二选定字线。 驱动电路向第一解码电路，第二解码电路，第三解码电路，第一本地驱动电路和第二本地驱动电路提供一系列升压电压。

公开(公告)号：US06285583B1

公开(公告)日：2001-09-04

申请号：US09506351

申请日：2000-02-17

申请人： Lee Edward Cleveland ,  Kendra Nguyen

发明人： Lee Edward Cleveland ,  Kendra Nguyen

IPC分类号： G11C1604

CPC分类号： G11C16/22

摘要： A flash memory device (100) includes a core cell array including two banks (194, 196) of core cells and address decoding circuitry (112, 114, 118, 120) and a write protect circuit. The write protect circuit includes sector write protect circuits (210) associated with respective sectors (202) of the core cell array in storing write protect data for the associated sector. The write protect circuit further includes a switch circuit (404) which selects one sector write protect signal in response to a write select signal to produce a combined write protect signal. The write protect circuit further includes an output circuit (406) coupled to the switch circuit to produce a sector write protect signal.

摘要翻译： 闪存器件（100）包括核心单元阵列，其包括核心单元的两个组（194,196）和地址解码电路（112,114,118,120）和写保护电路。 写保护电路包括与存储关联扇区的写保护数据相关联的与核心单元阵列的相应扇区（202）相关联的扇区写保护电路（210）。 写保护电路还包括开关电路（404），其响应于写选择信号选择一个扇区写保护信号以产生组合写保护信号。 写保护电路还包括耦合到开关电路以产生扇区写保护信号的输出电路（406）。

公开(公告)号：US06243316B1

公开(公告)日：2001-06-05

申请号：US09501159

申请日：2000-02-09

申请人： Takao Akaogi ,  Ali K. Al-Shamma ,  Lee Edward Cleveland ,  Yong Kim ,  Jin-Lien Lin ,  Boon Tang Teh ,  Kendra Nguyen

发明人： Takao Akaogi ,  Ali K. Al-Shamma ,  Lee Edward Cleveland ,  Yong Kim ,  Jin-Lien Lin ,  Boon Tang Teh ,  Kendra Nguyen

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C16/08

摘要： A voltage boost circuit (111) for a memory (100) includes a boosting circuit (110) which is coupled to a boosted node (120) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (112) coupled to the boosted node and including a switchable zero-threshold transistor (202) for resetting the boosted node to a reset voltage (VCC).

摘要翻译： 用于存储器（100）的升压电路（111）包括升压电路（110），其被耦合到升压节点（120）以升高用于访问存储器的核心单元的字线电压。 升压电路还包括耦合到升压节点的复位电路（112），并且包括用于将升压节点复位到复位电压（VCC）的可切换零阈值晶体管（202）。

公开(公告)号：US06229735B1

公开(公告)日：2001-05-08

申请号：US09638055

申请日：2000-08-11

申请人： Takao Akaogi ,  Kendra Nguyen ,  Yong Kim ,  Lee Cleveland

发明人： Takao Akaogi ,  Kendra Nguyen ,  Yong Kim ,  Lee Cleveland

IPC分类号： G11C1606

CPC分类号： G11C8/18 ,  G11C8/08

摘要： A burst read mode operation is provided that boosts the voltage of a word line while the bit lines of the row are selected for reading. When the column group address bits read the last column group of cells in the row, a pulse signal is generated which temporarily reduces the boosted voltage to allow the X-decoder to select the next word line. An alternative delay element is also provided which generates an ATD pulse with a longer duration when the column group address bits are at the end of a row and a shorter duration pulse at other times.

摘要翻译： 提供突发读取模式操作，其提高字线的电压，同时选择行的位线用于读取。 当列组地址位读取行中的最后一列单元格时，产生脉冲信号，临时降低升压电压，以允许X解码器选择下一个字线。 还提供了另一种延迟元件，当列组地址位在行的末尾，而在其他时间具有较短的持续时间脉冲时，其产生具有较长持续时间的ATD脉冲。