Semiconductor device with alternating conductivity type layer and method of manufacturing the same

发明授权

US06291856B1 Semiconductor device with alternating conductivity type layer and method of manufacturing the same 有权

标题翻译：具有交替导电型层的半导体器件及其制造方法

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专利标题： Semiconductor device with alternating conductivity type layer and method of manufacturing the same
专利标题（中）： 具有交替导电型层的半导体器件及其制造方法
申请号： US09438078

申请日： 1999-11-10
公开(公告)号： US06291856B1

公开(公告)日： 2001-09-18
发明人: Yasushi Miyasaka , Tatsuhiko Fujihira , Yasuhiko Ohnishi , Katsunori Ueno , Susumu Iwamoto
申请人： Yasushi Miyasaka , Tatsuhiko Fujihira , Yasuhiko Ohnishi , Katsunori Ueno , Susumu Iwamoto
优先权： JP10-321567 19981112; JP11-221861 19990805
主分类号： H01L2976
IPC分类号： H01L2976

Semiconductor device with alternating conductivity type layer and method of manufacturing the same

摘要：

This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.

摘要（中）：

本发明澄清了参数的影响，并且能够批量生产具有在导通状态下导通电并且耗尽OFF状态的并联pn层构成的漂移层的超结半导体器件。 n个漂移区域中的杂质量在p分配区域中的杂质量的100％至150％之间或110％至150％的范围内。 n个漂移区域和p个分割区域中的任一个的杂质浓度在其他区域的杂质浓度的92％〜108％的范围内。此外，n个漂移区域和p个分割区域中的任一个的宽度在其他区域的宽度的94％和106％之间的范围内。

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