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公开(公告)号：US07872282B2
公开(公告)日：2011-01-18
申请号：US12365159
申请日：2009-02-03
申请人： Susumu Iwamoto , Takashi Kobayashi
发明人： Susumu Iwamoto , Takashi Kobayashi
IPC分类号： H01L29/74 , H01L31/111 , H01L29/76 , H01L29/94 , H01L27/108
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404 , H01L29/7393
摘要： A semiconductor device includes deep first field limiting rings, shallow second field limiting rings, insulation films covering each surface portion of each of the first and the second field limiting rings, and conductive field plates each in contact with a surface of each of the first and the second field limiting rings. Each of the field plates project over a surface of each of the insulation films between the first field limiting rings and the second field limiting rings.
摘要翻译： 半导体器件包括深第一场限制环，浅第二场限制环，覆盖第一和第二场限制环中的每一个的每个表面部分的绝缘膜，以及每个与第一和第二场限制环中的每一个的表面接触的导电场板 第二场限制环。 每个场板在第一场限制环和第二场限制环之间的每个绝缘膜的表面上突出。
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公开(公告)号：US20090194786A1
公开(公告)日：2009-08-06
申请号：US12365159
申请日：2009-02-03
申请人： Susumu IWAMOTO , Takashi KOBAYASHI
发明人： Susumu IWAMOTO , Takashi KOBAYASHI
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404 , H01L29/7393
摘要： A semiconductor device includes deep first field limiting rings, shallow second field limiting rings, insulation films covering each surface portion of each of the first and the second field limiting rings, and conductive field plates each in contact with a surface of each of the first and the second field limiting rings. Each of the field plates project over a surface of each of the insulation films between the first field limiting rings and the second field limiting rings.
摘要翻译： 半导体器件包括深第一场限制环，浅第二场限制环，覆盖第一和第二场限制环中的每一个的每个表面部分的绝缘膜，以及每个与第一和第二场限制环中的每一个的表面接触的导电场板 第二场限制环。 每个场板在第一场限制环和第二场限制环之间的每个绝缘膜的表面上突出。
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公开(公告)号：US07262459B2
公开(公告)日：2007-08-28
申请号：US11054366
申请日：2005-02-09
申请人： Kouta Takahashi , Susumu Iwamoto
发明人： Kouta Takahashi , Susumu Iwamoto
IPC分类号： H01L29/76
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0696 , H01L29/7811
摘要： An active region in a semiconductor device is made up of a parallel p-n layer including a first p-semiconductor layer and a first n-semiconductor with the widths and total amounts of impurities being equal to each other to provide a structure in which charges are balanced. A section parallel to stripes in the parallel p-n layer in an inactive region is made up of a second parallel p-n layer including a second p-semiconductor layer, with its width larger than that of the first p-semiconductor layer, and a second n-semiconductor layer with its width smaller than that of the first n-semiconductor layer. The total amount of impurities in the second p-semiconductor layer is made larger than that in the second n-semiconductor layer to provide a structure in which charges are made unbalanced.
摘要翻译： 半导体器件中的有源区域由包括第一p半导体层和第一n半导体的并行pn层构成，其中杂质的宽度和总量彼此相等，以提供电荷平衡的结构 。 在非活性区域中与平行pn层中的条纹平行的部分由包括第二p半导体层的第二平行pn层构成，其宽度大于第一p半导体层的宽度， 半导体层的宽度小于第一n半导体层的宽度。 第二p半导体层中的杂质总量比第二n半导体层中的杂质总量大，以提供不均衡电荷的结构。
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公开(公告)号：US07042046B2
公开(公告)日：2006-05-09
申请号：US10925407
申请日：2004-08-25
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.
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公开(公告)号：US07029977B2
公开(公告)日：2006-04-18
申请号：US10792884
申请日：2004-03-05
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/0634 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/3065 , H01L29/045 , H01L29/0688
摘要： A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
摘要翻译： 半导体晶片的制造方法可以用具有高晶体质量的外延膜填充在半导体衬底中形成的沟槽，而不会在沟槽中留下空洞。 沟槽形成在第一导电型半导体衬底中。 通过将衬底放置在气体炉中，然后向炉内供应蚀刻气体和载气，并且通过在沟槽内的暴露平面上蚀刻约几纳米的厚度，将暴露在沟槽内的平面制成干净的表面 至一微米。 沟槽具有通过蚀刻向上的几何形状。 在蚀刻之后，通过向炉提供生长气体，蚀刻气体，掺杂气体和载气，从而在沟槽中外延生长第二导电型半导体，由此填充沟槽。 不是使沟槽向上略微打开，它们的侧壁可以制成使得能够形成小平面的平面。
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公开(公告)号：US07002205B2
公开(公告)日：2006-02-21
申请号：US10735501
申请日：2003-12-12
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.
摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。
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公开(公告)号：US06586801B2
公开(公告)日：2003-07-01
申请号：US09845747
申请日：2001-05-01
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095
摘要： A semiconductor device facilitates preventing hot carriers from being injected into the insulation film so that the characteristics and the reliability of the active region thereof may not be impaired. The device includes an alternating-conductivity-type drain including heavily doped p-type breakdown voltage limiter regions in the portions of p-type partition regions in contact with the well bottoms of p-type base regions. Since the electric field in the central portion of breakdown voltage limiter regions reaches the critical value in advance to the electric field at the points E beneath gate insulation films the electric field at the points E is relaxed and hot carrier injection into gate insulation films is prevented.
摘要翻译： 半导体器件有助于防止热载流子注入到绝缘膜中，使得其有源区的特性和可靠性不会受损。 该器件包括在与p型基极区的阱底部接触的p型分隔区的部分中包括重掺杂p型击穿电压限制区的交流导电型漏极。 由于击穿电压限制器区域的中心部分的电场预先到达栅极绝缘膜下面的点E处的电场的临界值，所以点E处的电场被放宽，并且阻止了热载流子注入到栅极绝缘膜中 。
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公开(公告)号：US06724042B2
公开(公告)日：2004-04-20
申请号：US09781066
申请日：2001-02-09
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.
摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。
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公开(公告)号：US06700141B2
公开(公告)日：2004-03-02
申请号：US09978847
申请日：2001-10-17
IPC分类号： H01L2936
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/7802
摘要： A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.
摘要翻译： 提供了可靠的超结半导体器件，其有助于放松导通电阻和击穿电压之间的折衷关系，并提高在感性负载下的雪崩耐受能力。 超结半导体器件包括在第一交替导电型层和n ++类漏极层之间包括薄的第一交替导电型层和重掺杂n +型中间漏极层的有源区，以及 包括厚的第二交替导电类型层的击穿耐受区域。 或者，有源区包括第一交替导电类型层和第n +型漏极之间的第一交变导电类型层和第三交变导电类型层，第三交变导电类型层比第一交变导电类型层更重掺杂 。
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公开(公告)号：US06677643B2
公开(公告)日：2004-01-13
申请号：US09811727
申请日：2001-03-19
IPC分类号： H01L2976
CPC分类号： H01L21/26513 , H01L21/266 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other. The second alternating conductivity type layer including regions of the first conductivity type and regions of the second conductivity type arranged alternately with each other. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer.
摘要翻译： 提供了一种能够容易地进行批量生产，降低导通电阻和击穿电压之间的折衷关系的超结半导体，获得高的击穿电压并降低导通电阻以增加其电流容量。 超结半导体器件包括具有第一主表面和面向第一主表面的第二主表面的半导体芯片; 在第二主表面侧具有低电阻的层; 低电阻层上的第一交替导电类型层和第一交变导电类型层上的第二交变导电类型层。 第一交变导电类型层包括彼此交替排列的第一导电类型的区域和第二导电类型的区域。 包括第一导电类型的区域和第二导电类型的区域的第二交替导电类型层彼此交替排列。 第二交变导电类型层中的pn结之间的间隔比第一交变导电类型层中的pn结之间的间隔宽。
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