Invention Grant
- Patent Title: Clocked logic gate circuit
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Application No.: US09725812Application Date: 2000-11-30
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Publication No.: US06316961B2Publication Date: 2001-11-13
- Inventor: Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
- Applicant: Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Noboru Masuda , Kenji Kaneko , Makoto Hanawa , Takeshi Kusunoki
- Priority: JP8-249587 19960920
- Main IPC: H03K19096
- IPC: H03K19096

Abstract:
A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.
Public/Granted literature
- US20010000017A1 Clocked logic gate circuit Public/Granted day:2001-03-15
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