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    Multiprocessor system having a processor invalidating operand cache when lock-accessing
    2.
    发明授权
    Multiprocessor system having a processor invalidating operand cache when lock-accessing 失效
    具有处理器的多处理器系统在锁定访问时使操作数缓存无效

    公开(公告)号：US5740401A

    公开(公告)日：1998-04-14

    申请号：US9077

    申请日：1993-01-26

    申请人： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

    发明人： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

    IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F12/08 ,  G06F12/14 ,  G06F15/177

    CPC分类号： G06F9/52 ,  G06F12/0806 ,  G06F12/1466

    摘要： A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.

    摘要翻译： 多处理器系统包括地址总线170，数据总线180，处理器110和120，访问队列135和145，共享存储器130和140以及锁定控制电路500和510.特别地，锁定指示标志寄存器501是 当一个处理器110中的操作数高速缓存112正在对共享存储器130的预定地址进行锁定访问时，标志寄存器501是基于锁定命令信号260设置的， 在另一个处理器120中的指令高速缓存122到共享存储器130的预定地址的访问是被禁止的，但是在锁定访问时允许访问不同的地址。 在锁定访问被释放之后，锁定控制电路500接受对预定地址的访问。

    Pass transistor type selector circuit and digital logic circuit
    3.
    发明授权
    Pass transistor type selector circuit and digital logic circuit 失效
    通过晶体管型选择电路和数字逻辑电路

    公开(公告)号：US5572151A

    公开(公告)日：1996-11-05

    申请号：US511802

    申请日：1995-08-07

    申请人： Makoto Hanawa ,  Kenji Kaneko ,  Noriyasu Ido

    发明人： Makoto Hanawa ,  Kenji Kaneko ,  Noriyasu Ido

    IPC分类号： H03K19/20 ,  G06F7/50 ,  G06F7/509 ,  G06F7/60 ,  H03K17/693 ,  H03K19/0944 ,  H03K19/173

    CPC分类号： G06F7/509 ,  G06F7/607 ,  H03K17/693 ,  H03K19/1737

    摘要： A pass transistor type selector circuit comprises a control signal supplying circuit for supplying a pair of control signals of opposite phases to the respective gate electrodes of a pair of nMOS transistors of a selecting circuit. The control signal supplying circuit includes a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal is low level. The control signal interrupting means is provided with a discharging means for discharging high-level one of the gate electrodes of the nMOS transistors of the signal selecting circuit while the clock signal is low level. The discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of the signal selecting circuit and a grounding terminal.

    摘要翻译： 传输晶体管型选择器电路包括控制信号提供电路，用于将一对相反相位的控制信号提供给选择电路的一对nMOS晶体管的各个栅电极。 控制信号提供电路包括与时钟信号同步工作的控制信号中断装置，以便在时钟信号为低电平时有选择地中断向信号选择电路提供控制信号。 控制信号中断装置设置有用于在时钟信号为低电平时对信号选择电路的nMOS晶体管的高电平一个栅电极进行放电的放电装置。 放电装置包括两个nMOS晶体管，每个晶体管连接在信号选择电路的nMOS晶体管的各个栅电极和接地端子之间。

    Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit
    5.
    发明授权
    Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit 失效
    单芯片流水线数据处理器采用指令和操作数缓存存储器，用于并行操作指令控制和执行单元

    公开(公告)号：US4989140A

    公开(公告)日：1991-01-29

    申请号：US323125

    申请日：1989-03-13

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/38 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F13/16 ,  G06F15/78

    CPC分类号： G06F9/30047 ,  G06F12/0848 ,  G06F12/0891 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824

    摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

    摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有从主存储器读出的第一相关存储器存储指令，以及指令控制器，当该指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的指令的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。

    Method and a device for allowing only a specific kind of hardware to correctly execute software
    6.
    发明申请
    Method and a device for allowing only a specific kind of hardware to correctly execute software 失效
    方法和仅允许特定类型的硬件正确执行软件的设备

    公开(公告)号：US20060070057A1

    公开(公告)日：2006-03-30

    申请号：US11235271

    申请日：2005-09-27

    申请人： Momoto Watanabe ,  Hiroaki Sano ,  Makoto Hanawa

    发明人： Momoto Watanabe ,  Hiroaki Sano ,  Makoto Hanawa

    IPC分类号： G06F9/44

    CPC分类号： G06F21/57 ,  G06F9/445

    摘要： A method of limiting the use of software determines, before the software is executed on hardware, whether or not the hardware has a specific configuration inherent in a specific kind of hardware. If it is determined that the hardware has the specific configuration, then the method allows the software to be executed on that hardware. Otherwise, the method runs the software with a penalty incorporated therein such as to substantially be unusable. This allows the software to be correctly executed only by the specific kind of hardware.

    摘要翻译： 在软件在硬件上执行之前，限制软件的使用的方法确定硬件是否具有特定类型硬件中固有的特定配置。 如果确定硬件具有特定配置，则该方法允许在该硬件上执行软件。 否则，该方法运行软件，其中纳入其中的惩罚，基本上不可用。 这使得软件只能由特定类型的硬件正确执行。

    Clocked logic gate circuit
    7.
    发明授权
    Clocked logic gate circuit 有权
    时钟逻辑门电路

    公开(公告)号：US06476644B2

    公开(公告)日：2002-11-05

    申请号：US09725450

    申请日：2000-11-30

    申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

    发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

    IPC分类号： G11C800

    CPC分类号： H03K19/0963 ,  H03K19/1738

    摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

    摘要翻译： 构成时钟逻辑门电路，使得开关单元由逻辑块和参考MOS晶体管构成，参考MOS晶体管的源极连接到逻辑块的一个输出端，参考MOS晶体管的栅极被连接 到逻辑块的另一个输出端，构成逻辑块的MOS晶体管（输入晶体管）并联连接。 通过这种布置，不需要互补的输入，并且驱动MOS晶体管和输入晶体管（或驱动MOS晶体管和参考MOS晶体管）可以串联连接。 结果，获得比构成便利的双轨逻辑简单的电路，并且可以以比CMOS逻辑电路和路径晶体管逻辑电路更高的速度工作。

    Data processor
    8.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US06272596B1

    公开(公告)日：2001-08-07

    申请号：US09396414

    申请日：1999-09-15

    申请人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    发明人： Tadahiko Nishimukai ,  Atsushi Hasegawa ,  Kunio Uchiyama ,  Ikuya Kawasaki ,  Makoto Hanawa

    IPC分类号： G06F1202

    CPC分类号： G06F9/30047 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3824 ,  G06F12/0848 ,  G06F12/0891

    摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

    摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的指令的输出。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。

    Asynchronous signal synchronizing circuit
    10.
    发明授权
    Asynchronous signal synchronizing circuit 失效
    异步信号同步电路

    公开(公告)号：US4745302A

    公开(公告)日：1988-05-17

    申请号：US812349

    申请日：1985-12-23

    申请人： Makoto Hanawa ,  Kouki Noguchi ,  Osamu Shinbo

    发明人： Makoto Hanawa ,  Kouki Noguchi ,  Osamu Shinbo

    IPC分类号： H03K3/356 ,  H03K5/135 ,  H04L5/24 ,  H04L7/02 ,  H03K13/03 ,  H03K5/00

    CPC分类号： H04L7/02 ,  H03K3/356104 ,  H03K5/135 ,  H04L5/24

    摘要： An asynchronous signal synchronizing circuit for sampling and external asynchronous signal in a quarter of the period of a clock. A first latch circuit latches asynchronous input signal in accordance with a first clock, and a second latch circuit latches the output of the first latch circuit in accordance with a second clock having a phase shift 180.degree. out of phase with the first clock. A third latch circuit latches the output signal of the second latch signal in accordance with a clock signal that represents the inverse of the first clock. A fourth latch circuit latches the output signal of the third latch circuit under the control of a clock that corresponds to the inverse of the second clock. The asynchronous input signal is sampled at the tailing edge of the first clock signal and validated by the tailing edge of the second clock signal. The synchronization of the asynchronous signal can thus be performed in a quarter of a clock cycle.

    摘要翻译： 一个异步信号同步电路，用于在时钟周期的四分之一内采样和外部异步信号。 第一锁存电路根据第一时钟锁存异步输入信号，并且第二锁存电路根据具有与第一时钟异相180°相移的第二时钟来锁存第一锁存电路的输出。 第三锁存电路根据表示第一时钟的倒数的时钟信号来锁存第二锁存信号的输出信号。 第四锁存电路在对应于第二时钟的倒数的时钟的控制下锁存第三锁存电路的输出信号。 异步输入信号在第一时钟信号的尾部边缘进行采样，并由第二个时钟信号的尾部边缘进行验证。 因此异步信号的同步可以在四分之一时钟周期内执行。