公开(公告)号：US06826109B2

公开(公告)日：2004-11-30

申请号：US10345186

申请日：2003-01-16

申请人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

发明人： Shigeru Nakahara ,  Satoshi Iwahashi ,  Takeshi Suzuki ,  Keiichi Higeta ,  Kazuo Kanetani

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/104

摘要： The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.

摘要翻译： 本发明提供了一种半导体集成电路装置，其上安装有能够选择适于提高易用性，易于使用或低功耗或选择输入设定值的操作模式的RAM宏。 在RAM宏的第一操作模式中，接收输入信号的定时被设置为第一定时。 在第二操作模式中，将接收输入信号的定时设置为晚于第一定时的第二定时。 在包括用于接收输入信号的输入电路和用于对输入电路的输出信号进行解码的解码器电路的半导体集成电路装置中，基于第一信号激活输入电路，并且解码器电路基于 的第二信号。

公开(公告)号：US06369617B1

公开(公告)日：2002-04-09

申请号：US09437268

申请日：1999-11-10

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： G11C800

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数 用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为 减少 通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加 的周期被启用。

公开(公告)号：US06316961B2

公开(公告)日：2001-11-13

申请号：US09725812

申请日：2000-11-30

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Noboru Masuda ,  Kenji Kaneko ,  Makoto Hanawa ,  Takeshi Kusunoki

IPC分类号： H03K19096

CPC分类号： H03K19/0963 ,  H03K19/1738

摘要： A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

公开(公告)号：US5398201A

公开(公告)日：1995-03-14

申请号：US53330

申请日：1993-04-28

申请人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

发明人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C11/34

CPC分类号： G11C7/1057 ,  G11C5/147 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.

摘要翻译： 一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。 根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流 只有写入位线才能连接。 根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。 此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。 还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

公开(公告)号：US20080072095A1

公开(公告)日：2008-03-20

申请号：US11936543

申请日：2007-11-07

申请人： Hiroaki Nambu ,  Masao Shinozaki ,  Kazuo Kanetani ,  Hideto Kazama

发明人： Hiroaki Nambu ,  Masao Shinozaki ,  Kazuo Kanetani ,  Hideto Kazama

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC分类号： G11C11/413 ,  G06F1/04 ,  G11C11/419

摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

摘要翻译： 提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。 半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。 产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

公开(公告)号：US07233045B2

公开(公告)日：2007-06-19

申请号：US10960985

申请日：2004-10-12

申请人： Takemi Negishi ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Hideto Kazama

发明人： Takemi Negishi ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Hideto Kazama

IPC分类号： H01L23/62

CPC分类号： H01L27/0251 ,  H01L27/0259 ,  H01L2924/0002 ,  H03K19/00315 ,  H01L2924/00

摘要： Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal. The system also includes a second semiconductor device corresponding to the first input circuit and a third semiconductor device corresponding to the second input circuit.

公开(公告)号：US06998878B2

公开(公告)日：2006-02-14

申请号：US10754596

申请日：2004-01-12

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

IPC分类号： H03K19/20

CPC分类号： G11C8/10

摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中， 在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是 减少 利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期 增加。

公开(公告)号：US20050111265A1

公开(公告)日：2005-05-26

申请号：US11023395

申请日：2004-12-29

申请人： Kazuo Kanetani ,  Hiroaki Nambu

发明人： Kazuo Kanetani ,  Hiroaki Nambu

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C11/34 ,  H03K19/096 ,  G11C5/00

CPC分类号： G11C8/10

摘要： It is an object of the invention to provide a circuit configuration wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signal Φ1 and the decoder control signal Φ2, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.

摘要翻译： 本发明的目的是提供一种电路配置，其中在地址缓冲器控制信号Phi 1和解码器控制信号Phi 2之间不需要解码器控制信号Phi 2，从而在解码器电路的操作中实现加速。 该目的通过采用其中缓冲器与解码器集成的配置来实现，使得组成地址缓冲器的晶体管的输出电流路径和构成解码器的晶体管的输出电流路径彼此串联连接，从而形成 解码器输出的输出电流路径。 利用本发明，可以实现解码器电路的操作加速，低功耗和更高的周期。 此外，在使用半导体存储器中的解码器电路的情况下，可以参考半导体存储器来实现访问时间的缩短，低功耗和更高的周期。

公开(公告)号：US06842394B2

公开(公告)日：2005-01-11

申请号：US10261583

申请日：2002-10-02

申请人： Kazuo Kanetani ,  Hiroaki Nambu

发明人： Kazuo Kanetani ,  Hiroaki Nambu

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C11/34 ,  H03K19/096 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A high-speed, reduced power consumption address decoder circuit, wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signalΦ1 and the decoder control signal Φ2, thereby implementing speed-up in operation of a decoder circuit. Improved speed and reduced power consumption are attained by a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.

摘要翻译： 一种高速，低功耗地址解码器电路，其中在地址缓冲器控制信号Phi1和解码器控制信号Phi2之间不需要解码器控制信号Phi2，从而在解码器电路的操作中实现加速。 通过将缓冲器与解码器集成而构成地址缓冲器的晶体管的输出电流路径和组成解码器的晶体管的输出电流路径串联连接，可以实现提高速度和降低功耗， 从而形成解码器输出的输出电流路径。 利用本发明，可以实现解码器电路的操作加速，低功耗和更高的周期。 此外，在使用半导体存储器中的解码器电路的情况下，可以参考半导体存储器来实现访问时间的缩短，低功耗和更高的周期。

公开(公告)号：US06438050B1

公开(公告)日：2002-08-20

申请号：US10038914

申请日：2002-01-08

申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Fumihiko Arakawa

发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Fumihiko Arakawa

IPC分类号： G11C700

CPC分类号： H03K3/356139

摘要： A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.

摘要翻译： 一种用于通过信号线在电路单元之间传输数据信号的传输电路。 发送数据信号，用于在预充电期间将信号线预充电到高电位，并根据在评估期间传输的数据将其放电到低电位，或保持信号线原样。 锁存型源耦合逻辑被配置为使得用作下一级的输出端的第一节点和第二节点在预充电周期期间分别充电到高电位。 第二节点在评估期间根据第一节点的电位放电，第一节点根据信号线上的电位放电。 因此，可以加快由驱动电路对信号线进行放电的动作。